Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Questa
Edited by the Electronicstalk Editorial
Team on 18 May 2005
Single-kernel verification engine does
the lot
The new Questa line of verification products offer built-in support for testbench automation, coverage-driven verification, assertion-based verification and transaction-level modelling.
The new Questa line of verification products from Mentor Graphics offer built-in support for testbench automation, coverage-driven verification (CDV), assertion-based verification (ABV) and transaction-level modelling (TLM) This initial release includes two new products: Questa SystemVerilog and Questa Advanced Functional Verification (AFV)
This article was originally published on Electronicstalk on 9 May 2006 at 8.00am (UK)
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The Questa verification solution combines tools, methodology and industry partners to deliver a new level of verification productivity and efficiency to today's designers.
Functional verification expands in scope
Platform addresses low-power verification and incorporates verification management capabilities that enable closed-loop management reporting, analysis and documentation.
Both products use a new verification technology, QuestaSim, the first standards-based, single-kernel verification engine that integrates an HDL simulator, a constraint solver, an assertion engine, functional coverage and a common user interface.
"Every survey indicates that verification remains a huge bottleneck in design cycles, and it's clear that the industry must transition to new verification methodologies to eliminate the bottleneck", stated Robert Hum, Vice President and General Manager of Mentor Graphics Design Verification and Test Division.
"With Questa, designers can use the latest language standards and methodologies to find more bugs faster and increase verification productivity".
Further reading
Debug environment speeds ASIC validation
Isolating the cause of a failing processor driven test is a tedious and time consuming process, as RTL processor models delivered by the core vendor provide little or no debug visibility.
Mentor Graphics and UMC deliver IC design kits
Mentor Graphics and UMC have joined to deliver a complete turnkey design flow, including the availability of IC design kits, for UMC's RF and analogue/mixed-signal process technologies.
Mentor supports TI DSPs and MCUs
Mentor Graphics is the first to reach agreement with Texas Instruments to deliver coverification processor support packages (PSPs) for Texas Instruments DSP and microcontroller solutions.
Over the last two years, several new languages targeted at verification have been standardised.
The availability of these languages - SystemVerilog, SystemC and PSL - enables design teams to now move to new methodologies like CDV, ABV or TLM without the risk of getting stuck with proprietary languages or solutions.
According to Cliff Cummings, President of Sunburst Design, and an industry expert on Verilog and SystemVerilog: "We recognise the importance of SystemVerilog as the standard for system-level verification, which will enable a variety of verification methods throughout the design flow".
"We believe Mentor's Questa solution will increase the adoption of SystemVerilog for advanced verification".
Questa SystemVerilog incorporates the key components of the emerging IEEE P1800 SystemVerilog standard - design constructs, testbench constructs, assertions and the Direct Programming Interface (DPI) - into a single-kernel verification solution.
Verilog users now have a standards-based path to the new verification methodologies ensuring future reuse and design portability.
The integrated solution also offers performance and debugging advantages over the multiple-tool, multiple-language solutions users have to put together today.
Questa AFV provides support for SystemVerilog, VHDL, PSL and SystemC in a single-kernel verification solution.
Targeted at mixed-language flows, Questa AFV enables designers to choose the languages that best address their needs.
VHDL users will benefit greatly from tight links to the SystemVerilog verification capabilities for constrained-random testbench generation and functional coverage.
The Questa products represent the newest addition to Mentor's scalable verification solutions.
Questa AFV and Questa SystemVerilog are the first of a series of new verification solutions.
Questa products integrate with existing Mentor Graphics products to create customised solutions for specific methodologies.
ModelSim users can easily add Questa functionality with add-on options, and the Seamless, Advance MS, 0-In and VStation product lines are compatible with the new Questa products.
The Questa AFV platform will ship in Q2 2005 and is listed at US $42,000 for a perpetual licence.
Questa SystemVerilog, will also ship in Q2 2005 and is listed at $28,000 perpetual.
Term pricing is available.
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