Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 13 June 2005
Panasonic signs up for high-level
synthesis tools
Panasonic Communications has selected the Mentor Graphics Catapult C Synthesis tool after evaluating leading high-level synthesis tools.
Panasonic Communications has selected the Mentor Graphics Catapult C Synthesis tool after evaluating leading high-level synthesis tools Panasonic Communications chose the Catapult C Synthesis tool based on the product's maturity and the productivity improvements it offers by synthesising pure ANSI C++ descriptions
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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"During our evaluation, we found Catapult C's quality of results and ease-of-use to be very convincing", said Dr Akitoshi Matsuda, Corporate Information Systems Group, Panasonic Communications.
"Using the tool, we are able to realise the benefits of algorithmic synthesis, which uses pure ANSI C++ system models as input".
"Algorithmic synthesis requires far less manual effort, allowing us to specify interfaces and hierarchy using constraints, and instantly target FPGA or ASIC implementations without changing the original pure C++ source".
Panasonic Communications designs application specific integrated circuits (ASICs) used in their voice, data and video communication systems.
The company typically implements its algorithmic designs in a field programmable gate array (FPGA) prototype for real-time performance and functional validation before retargeting the design to an ASIC for production.
The manual effort required to create register-transfer level (RTL) descriptions for both FPGA prototypes and ASICs left no time for design exploration, leading the company to explore high-level synthesis.
The Catapult C Synthesis tool is the only product to automatically create RTL from a pure ANSI C++ source where both the core algorithm and interface are untimed.
This productivity improvement gives designers time to perform detailed "what-if" analysis on varying micro-architecture and interface scenarios to quickly achieve fully optimised hardware designs for either FPGA or ASIC implementations.
The tool creates RTL that can be synthesised into gates using standard RTL synthesis products, enabling it to fit within a wide variety of tool flows.
"Panasonic Communications is an expert in using high-level synthesis tools to achieve time-to-market and quality goals for network terminal products", Simon Bloch, General Manager of Design Creation and Synthesis Division.
"We are honoured that such an outstanding company has selected Catapult C Synthesis as it deploys the benefits of algorithmic synthesis".
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