Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 13 June 2005
Scan test tool joins reference flow
Taiwan Semiconductor Manufacturing Company (TSMC) has added the TestKompress scan test tool to its Reference Flow 6.0.
Taiwan Semiconductor Manufacturing Company (TSMC) has added the TestKompress scan test tool to its Reference Flow 6.0 TestKompress provides an effective means of increasing volume manufacturing test quality and reducing test cost for nanometre designs
This article was originally published on Electronicstalk on 16 Jul 2001 at 8.00am (UK)
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Reference Flow 6.0 also includes Mentor Graphics DFT tool suiteFastscan, MBISTArchitect and BSDArchitect.
"Reference Flow 6.0 has added new design-for-test technologies that address specific nanometre needs", said Ed Wan, Senior Director of Design Service Marketing at TSMC.
"The Mentor Graphics TestKompress product provides increased test quality while reducing test data volume, test time, and test cost".
The Mentor Graphics TestKompress embedded deterministic test (EDTTM) tool reduces both manufacturing test time and test data volume by up to 100x, helping users increase test coverage and test quality on their complex devices.
This compression enables manufacturers to run a large battery of tests without slowing test time, thereby maintaining a low cost of test.
The tool also features robust x-state tolerance that eliminates the need to either add functional logic or adhere to strict design requirements imposed by the test structures.
In addition, the TestKompress tool fits well into any scan-based methodology, and features a usage methodology that is intuitive to engineers familiar with traditional ATPG.
Both TestKompress and FastScan feature advanced at-speed test capabilities to improve detection of speed-related defects found at smaller process technologies.
TSMC has also added the MBISTArchitect and BSDArchitect tools from Mentor Graphics to provide a complete design for test (DFT) toolset in Reference Flow 6.0.
MBISTArchitect provides at-speed test of embedded memories operating up to 1GHz; BSDArchitect is used to insert IEEE1149.1 boundary scan that enables in-circuit test.
"TSMC is an industry leader in meeting the challenges inherent in volume manufacturing of complex nanometre devices", said Robert Hum, Vice President and General Manager of the Design Verification and Test Division for Mentor Graphics.
"We are very pleased that Mentor DFT tools have been added to TSMC's Reference Flow 6.0 to meet the specific challenges of cost-effective nanometre production test and improve manufacturing test quality".
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