Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: HDL Designer Series
Edited by the Electronicstalk Editorial
Team on 10 October 2005
HDL design suite gains its own
spellchecker
Mentor Graphics has developed a novel concurrent design checking and creation environment, which is available in the latest version of the HDL Designer Series tool suite.
Mentor Graphics has developed a novel concurrent design checking and creation environment, which is available in the latest version of the HDL Designer Series tool suite Widely adopted as the most effective HDL design solution for ASICs and FPGAs, the comprehensive HDL Designer Series environment equally benefits individual engineers as well as large design teams, significantly reducing cycle times and respins
This article was originally published on Electronicstalk on 21 Sep 2001 at 8.00am (UK)
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HDL Designer Series 2001.5 is the latest version of the design creation and management tool suite from Mentor Graphics.
"From a company perspective, the overall benefit using HDL Designer Series is the increase in designer productivity", said Thierry Pfirsch, Competency Manager, Hardware Design Tools, Alcatel Worldwide.
"We have seen significant improvement in the time needed to capture, check, analyse, debug and document designs, in some cases up to five times faster than before".
With this new release, HDL Designer fully integrates the industry's first high-speed HDL design checking engine, optimised to operate in real time and concurrently during design creation.
Further reading
Interface-based design simplifies IC interconnects
The latest release of the HDL Designer Series tool suite from Mentor Graphics offers productivity enhancements including an improved interconnect table.
Software evolves to more complex designs
HDL Designer Series 2003.1 is the latest version of the industry-leading environment for the creation, development and management of complex ASIC and FPGA semiconductor designs.
FPGA software moves to a new level
The latest version of FPGA Advantage features a new design cockpit that integrates recent updates to the HDL Designer Series, ModelSim and Precision RTL Synthesis products.
The release also supports advanced design and verification languages such as SystemVerilog and Property Specification Language (PSL), and provides expanded documentation capabilities via Adobe Systems' Scalable Vector Graphics (SVG) output.
"Our primary motivation in acquiring HDL Designer Series was to gain access to its design entry and visualisation tools, which allow us to work a higher level than just VHDL or Verilog text entry", said Laurent Hausammann, Senior EE Engineer, ASIC Team Leader, Olivetti I-Jet.
"Using the tool's various features saves us many months of effort across the entire design cycle".
Immediately available for use by ASIC and FPGA design teams working with Verilog, SystemVerilog and VHDL design languages, the integrated static design checking functionality enables designers using HDL Designer to accurately analyse RTL code during design creation, where they can quickly identify and resolve rule violations that would otherwise cause respins in simulation and synthesis runs, or ultimately, respins in silicon.
"Concurrent design checking fundamentally changes the design paradigm".
"This is analogous to the way in which spelling and grammar checkers have changed the way we create written correspondence, sharply reducing the need for manual review", said Glenn Perry, General Manager, Design Creation Business Unit, Mentor Graphics.
"Our approach to concurrent design checking, combined with blazing fast speed of analysis and error isolation, enables companies to identify and rectify potential defects before they become more expensive to fix downstream".
Unlike traditional post-process, batch-oriented linting tools, the configurable, high-performance HDL checking features in HDL Designer are easy to use and extraordinarily fast, thus enabling real-time analysis.
The parameterised rule capability makes it far easier to configure the tool to do what any particular design team needs without initially spending a lot of time preparing rule sets.
Moreover, checking for design reusability when the code is originally written helps deliver the productivity promise of reuse, by reducing the need to change and re-verify the code for every subsequent design in which it is used.
The HDL Designer Series tool suite provides a complete enterprise-level HDL development platform for ASICs and FPGAs, which integrates easily into any existing design flow.
HDL Designer Series enables companies to scale organisational productivity, as well as engineering productivity, by providing an impressive array of technologies focused on design creation, analysis, checking, and management capabilities within a single tool.
HDL Designer Series is part of Mentor Graphics comprehensive FPGA Advantage design flow, which also includes the industry leading ModelSim and Precision Synthesis tools.
HDL Designer Series is available immediately with pricing starting at US $6400 for a node-locked licence and US $9600 for a floating licence.
HDL Designer Series is compatible with all major operating systems for maximum flexibility and ease of use.
The following platforms are currently supported: Linux Redhat/SuSE, Sun Solaris, HP-UX, and Windows 2000, XP and NT 4.0.
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