Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 30 January 2006
Japanese consortium collaborates on test
schemes
Mentor Graphics has signed a joint development agreement with STARC, a research and development consortium cofounded by 11 major Japanese semiconductor companies.
Mentor Graphics has signed a joint development agreement with STARC (the Semiconductor Technology Academic Research Centre), a research and development consortium cofounded by 11 major Japanese semiconductor companies The joint development will focus on new at-speed delay test methodologies for IC designs that will increase outgoing chip quality levels by improving the detection of small delay defects during manufacturing test
This article was originally published on Electronicstalk on 11 Apr 2002 at 8.00am (UK)
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As nanometre technology moves to the 90 and 65nm nodes, minor parametric variations give rise to an increase in delay-related defects in the manufacturing process.
Many of these defects are subtle deviations leading to small delay variations that are difficult to detect using standard delay test techniques.
To maintain high quality levels for tested devices, many advancements in at-speed test pattern generation technology have emerged.
The development partnership between Mentor and STARC seeks to fulfil proposed delay defect detection requirements from STARC and its client companies by incorporating new technologies into Mentor's automatic test pattern generation (ATPG) IC test tools that will ensure the highest quality for tested chips.
"STARC's mission is to seek out new and effective technologies through joint research between universities and the industry, in order to achieve breakthroughs in semiconductor technologies", said Yasuo Sato, Senior Manager, Test Methodology Group at STARC.
"As our member companies move to 90 and 65nm technologies, improving manufacturing test is a critical requirement".
"We believe that this partnership with Mentor will satisfy that requirement and will result in a breakthrough at-speed test methodology".
"The proposals from the STARC consortium for improving small delay defect detection coincides with Mentor's development efforts in the area of at-speed test pattern generation", said Robert Hum, Vice President and General Manager for the Design Verification and Test Division at Mentor Graphics.
"We are extremely pleased to be working closely with STARC, and look forward to continuing this development partnership to provide real solutions for STARC and our customers".
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