Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Calibre LFD
Edited by the Electronicstalk Editorial
Team on 03 April 2006
Design tools support Common Platform
Tools from the Calibre design-to-silicon platform are qualified and available to support design for the IBM/Chartered/Samsung 65nm process Common Platform technology.
Several best-in-class tools from the Calibre design-to-silicon platform are qualified and available to support a robust design for manufacturing (DFM) methodology for the IBM/Chartered/Samsung 65nm process Common Platform technology These production-proven tools further empower designers targeting the cross-foundry process to identify and address possible yield detractors early in the design flow, thereby improving the likelihood of successful yield in leading-edge nanometre technologies
This article was originally published on Electronicstalk on 28 Jul 2006 at 8.00am (UK)
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Mentor Graphics has validated its Calibre LFD (litho-friendly design) results in silicon on 65nm process technology.
Flexible foundry support for this new breed of DFM tools is imperative for the success of next generation IC design flows.
More specifically, Calibre LFD is the first production-proven EDA tool to address the urgent issue of how to manage lithographic process variability in the early stages of design creation.
Calibre LFD enables designers to make trade-off decisions on how to create a design that is more robust and less sensitive to the lithographic process window.
Further reading
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Mentor Graphics and UMC have joined to deliver a complete turnkey design flow, including the availability of IC design kits, for UMC's RF and analogue/mixed-signal process technologies.
Mentor supports TI DSPs and MCUs
Mentor Graphics is the first to reach agreement with Texas Instruments to deliver coverification processor support packages (PSPs) for Texas Instruments DSP and microcontroller solutions.
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Mentor Graphics and Xilinx have released two high-level IP products to accelerate the design cycle of high-density FPGAs in communications applications.
This is important at the 90nm technology node, and crucial at the 65nm node, where even small process variations can greatly influence silicon results.
An LFD kit is provided to the designer by the Common Platform manufacturing partners and is useable to target the common 65nm process from any of the three manufacturing facilities, much in the same manner as a design rule checking (DRC) kit.
The encrypted kit includes energy, dose and mask bias considerations; RET recipes, process models, and the parameterisable rules to be checked.
The designer can run simulations to see how a layout will perform under a particular lithographic process window.
The goal is to drive the design to an "LFD clean" as well as a "DRC clean" sign-off.
"IBM, Chartered and Samsung have worked closely with Mentor in the optimisation of Calibre LFD for the Common Platform technology at 65nm", said Steve Longoria, Vice President, Semiconductor Technology Platform for IBM Systems and Technology Group.
"The availability of this tool enhances our platform DFM suite and expands our open ecosystem based on collaboration and innovation".
"Design teams can explore lithographic sensitivities early in the design stages, and make critical decisions before the design is sent to fabrication in any of the three partners' respective facilities".
Calibre Yieldanalyser provides a comprehensive approach for the Common Platform to deliver a design-for-yield capability to customers.
Calibre YieldAnalyzer includes DFM rules that cover all key areas of yield loss such as random, systematic and parametric.
The Common Platform leads the industry in providing yield improvement metrics that show designers how and where they should spend their time to improve the yield of their designs.
The Common Platform uses the power of YieldAnalyzer to deliver their yield improvement metrics to customers in the form of a Calibre DFM deck, which provides designers a natural extension of DRC with DFM.
"The volume and complexity of 'signoff' rules at 65nm is staggering", said Ana Hunter, Vice President of Technology for Samsung Semiconductor: "This daunting task can be simplified and, through our co-operative efforts designers are empowered to evaluate tradeoffs, and get a relative idea of how each decision impacts yield themselves".
"Today, we've reached a major milestone in the adoption of new tools and technologies that address DFM, and we are pleased to be supporting the Common Platform model as a viable option for our customers", said Joe Sawicki, Vice President and General Manager for the Design-to-Silicon Division at Mentor Graphics.
"The infrastructure to manage the analysis and prevention of yield loss mechanisms is taking shape, and proving itself to be extremely valuable".
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