Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Questa 6.2
Edited by the Electronicstalk Editorial
Team on 09 May 2006
Functional verification moves to next
generation
The Questa verification solution combines tools, methodology and industry partners to deliver a new level of verification productivity and efficiency to today's designers.
Mentor Graphics has announced its comprehensive next-generation Questa verification solution, combining tools, methodology and industry partners to deliver a new level of verification productivity and efficiency to today's designers The announcements include the new Questa 6.2 functional verification platform, the industry's first open-source standards-based Advanced Verification Methodology (AVM), and the Questa Vanguard Programme (QVP), an organisation of over 25 companies dedicated to helping companies build more effective verification flows
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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"Tools by themselves don't solve problems", said Robert Hum, Vice President and General Manager of Mentor Graphics Design Verification and Test Division.
"You need standards, methodologies and an industry infrastructure that can get people up and running quickly with new capabilities".
"The new Questa solution addresses all of those requirements and is uniquely positioned to accelerate the adoption of the new flows that designers need".
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The new Advanced Verification Methodology (AVM) is the first true system-level-to-RTL verification methodology.
The AVM integrates advanced verification techniques like constrained-random stimulus, functional coverage and assertions into a single transaction level modelling (TLM)-based framework implemented in both SystemC and SystemVerilog.
Designed from the ground-up to take advantage of the new verification capabilities in SystemVerilog and SystemC, the AVM features an object-oriented coding style to reduce the amount of testbench code and a modular architecture to enable reuse.
The AVM consists of the AVM Cookbook, a "how-to" guide for getting started, and - an industry first - source code for base class libraries, utilities and implementation examples written in both SystemC and SystemVerilog.
The AVM code together with the AVM documentation will be provided under an Apache 2.0 open source licence.
"ARM is collaborating with Mentor on a number of items to ensure interoperability between ARM products and Mentor's EDA products", said Tim Holden, Director of EDA Relations, ARM.
"As such, our mutual customers will be able to take full advantage of a single kernel SystemVerilog/SystemC verification solution that offers performance and debugging advantages over the multitool, multilanguage solutions".
The Questa 6.2 platform is a mixed-language verification solution that supports simulation, assertions, coverage and testbench automation.
Questa 6.2 includes support for all of the key components of the AVM: the object-oriented and constrained-random capabilities of SystemVerilog and SystemC, the OSCI TLM standard functionality, and the functional coverage capabilities of SystemVerilog and PSL.
No other solution available today offers this broad support of advanced capabilities in standard languages.
Along with increases in performance and new capabilities in debugging, Questa 6.2 also includes the industry's first unified coverage database (UCDB).
The UCDB eliminates the complexity of gathering and managing coverage data and consolidates all of the verification coverage data generated by the Questa 6.2 platform (including other Mentor verification technologies, such as 0-In and Seamless tools).
With consolidated coverage analysis, designers can increase verification efficiency by identifying and eliminating wasted simulation cycles, quickly finding uncovered areas in the design, and close the verification loop by tying coverage results directly back to the original test plan.
Without adequate industry infrastructure, no new technologies or methodologies can be successful.
With the Questa Vanguard Programme (QVP), Mentor has joined forces with leaders in training, consulting and verification IP to simplify and accelerate the adoption of new verification languages and techniques.
Each vendor works closely with Mentor to ensure that their products support the Questa platform and the AVM.
"Today's and tomorrow's larger and more complex designs require innovative solutions".
"Verification remains the biggest bottleneck in design cycles making it necessary to transition to new methodologies and tools to remove the bottleneck", stated Predrag Markovic, CEO of HDL Design House.
"Questa offers a complete standards-based, single kernel verification environment that targets increasing verification productivity and enables the move to new methodologies like coverage-driven verification, assertion-based verification, and transaction level modelling".
"Questa incorporates the SystemVerilog standard, thus ensuring future reuse and design portability".
The Questa 6.2 verification platform will ship in Q2 2006 and includes access to the Advanced Verification Methodology portal.
Pricing starts at US $28,000.
The AVM will be available in Q2 2006 at no charge under a standard, open-source licence.
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