DFM technologies are qualified for 65nm process

An integrated set of best-in-class tools from the Calibre design-to-silicon platform supports TSMC's 65nm technology.

An integrated set of best-in-class tools from the Mentor Graphics Calibre design-to-silicon platform supports TSMC's 65nm technology.

This broad set of Calibre tools set the standard of excellence in terms of extending existing tools and platforms to address the issue of achieving acceptable yield in nanometre technologies.

The integrated DFM solution provided by the Calibre design-to-silicon platform includes functionality for litho-friendly design (Calibre LFD), critical area and recommended rule analysis (Calibre YieldAnalyzer), automated layout enhancements (Calibre YieldEnhancer), and DFM aware silicon modelling (Calibre xRC).

More specifically, the Calibre LFD tool addresses the urgent issue of how to manage lithographic process variability in the early stages of design creation.

Calibre LFD enables designers to make tradeoff decisions on how to create a design that is more robust and less sensitive to the lithographic process window.

This is important at the 90nm technology node, and crucial at the 65nm node, where even small process variations can greatly influence silicon results.

An LFD kit is provided to the designer much in the same manner as a design rule checking (DRC) kit.

The designer can run simulations to see how a layout will perform under a particular lithographic process window.

The designer benefits from being able to identify "hot-spots" during the layout creation stage.

The goal is to drive the design to an "LFD clean" as well as a "DRC clean" signoff.

"Calibre LFD provides an integrated approach to model based verification".

"This makes a difference in determining a layout topology that is optimised across process window conditions", said Ed Wan, Sr Director Design Services Division, TSMC.

Calibre YieldAnalyzer offers designers a single robust environment that facilitates the analysis of both critical area and recommended rules in the user's design environment.

These capabilities address the key sources of yield loss: random and systematic.

Designers can visualise the results of this model using graphical displays and data-driven tables to easily show them how and where they should spend time to improve yield.

This is done in the form of a Calibre DFM deck, giving designers a natural transition from a "golden" DRC deck to a "golden" DFM deck.

Calibre YieldEnhancer improves yield with automated layout enhancements that back annotate to industry standard design databases.

Specifically, it provides geometric manipulation to implement layout enhancements such as via doubling and expanding, extending and enlarging of polygons.

The goal is to improve yield without increasing area.

Calibre YieldEnhancer achieves this goal by leveraging Calibre's core DRC functionality to identify and take advantage of any available white space.

The result is a design that is "DRC clean" with higher yield.

"TSMC's 65nm design ecosystem represents a distinct approach to providing the support required to manage the analysis and prevention of yield loss in nanometre technology", said Joe Sawicki, Vice President and General Manager for the Design-to-Silicon Division at Mentor Graphics.

"It's exciting to see the rapid progress we've made with TSMC to qualify DFM technologies from Mentor".

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