Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Catapult SL
Edited by the Electronicstalk Editorial
Team on 15 June 2006
System level tool supports complex
designs
Catapult SL is billed as the first high-level synthesis tool to automatically create high-performance multiple-block subsystems from pure sequential ANSI C++.
Mentor Graphics has expanded its Catapult product line with Catapult SL (System Level), the first high-level synthesis tool to automatically create high-performance multiple-block subsystems from pure sequential ANSI C++ The Catapult SL tool supports complex hierarchical design, includes new technology that improves block-level performance and offers links to power analysis tools to help reduce power consumption by up to 30%
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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Designed with high-performance applications in mind, Catapult SL moves beyond block-level synthesis to automatically create entire signal processing subsystems tuned to the design's specific needs.
A hierarchical design engine enables Catapult SL to co-ordinate the operations of multiple blocks within the subsystem and automatically synthesise appropriate inter-block channels and memory buffers, leading to performance levels not easily achieved with hardware C languages or block-level synthesis methodologies.
Catapult SL also integrates carry-save adder, a design technique for streamlining computations and throughput to increase the performance of individual blocks.
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Carry-save adder functionality enables Catapult SL to create higher-performance hardware blocks while reducing hardware size.
In contrast, high-level synthesis tools that input hardware languages like SystemC require designers to embed structural details in their source code.
Manually inserting channels, memory buffers and interface timing not only requires more up-front design effort, it also effectively locks in a specific implementation and makes subsystem exploration impossible.
After conducting this time-consuming process, designers must live with performance bottlenecks in the form of suboptimal inter-block channel bandwidths and overbuilt memory buffers.
While this manual approach to subsystem design works for some applications, Catapult SL offers an automated way to eliminate these bottlenecks and achieve aggressive performance and time to market goals for high-performance video and wireless designs.
The latest member of the Catapult family also adds automated power analysis capabilities.
In customer usage, Catapult SL has demonstrated the ability to reduce power consumption by up to 30%.
Pushbutton links to leading third-party power analysis tools make it easy for designers to create multiple subsystem implementations with Catapult SL.
Designers can then quickly evaluate the different implementations to find the most power-efficient design.
Catapult SL also links to leading formal equivalence checking tools to verify correctness between pure ANSI C++ descriptions and RTL implementations, and to leading simulators, allowing automated evaluation of tradeoffs in functionality, performance and area.
"With data and video/imaging becoming standard in next-generation communications applications, many designers are hungry for higher signal-processing performance", said Simon Bloch, General Manager of the Mentor Graphics Design Creation and Synthesis Division.
"The new functionality provided by Catapult SL starts with the productivity improvements inherent in the Catapult family, and adds capacity and intelligent design techniques that will help bridge the performance gap between off-the-shelf DSPs and the needs of tomorrow's complex systems".
The initial member of the Catapult product family, Catapult C Synthesis, was the first to synthesise pure ANSI C++ to RTL.
Pure ANSI C++ is devoid of hardware constructs, allowing the Catapult tools to create RTL for both ASIC and FPGA technologies.
The Catapult tools' incremental design methodology gives the designer visibility and control during the entire synthesis process, allowing for interactive design exploration at every transformation.
Further, the Catapult tools' patent-pending interface synthesis technology automates a tedious manual design task by targeting a number of standard and proprietary hardware interfaces.
Finally, Catapult automatically generates SystemC transaction-level models (TLM) for high-speed simulation and system-level verification.
As a result, designers can perform detailed "what-if" analysis on varying micro-architecture and interface scenarios and achieve fully optimised hardware designs.
The Catapult tools' RTL output can be synthesised into gates using industry-standard RTL synthesis products, enabling it to fit within a wide variety of tool flows.
The Catapult SL tool is priced at $350,000, and is currently available in either term or perpetual licences.
Other members of the Catapult product family are priced starting at $140,000.
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