Design rule checker adapts to the nanometre era

Calibre nmDRC redefines traditional design rule checking by dramatically reducing total cycle time and integrating critical elements such as critical area analysis and critical feature identification.

Available now from Mentor Graphics, the Calibre nmDRC redefines the traditional design rule checking (DRC) step by dramatically reducing total cycle time and integrating critical elements such as critical area analysis and critical feature identification, all required to solve the yield challenges of the nanometre era.

Calibre nmDRC is part of a new platform from Mentor, the Calibre nm Platform.

This platform signals a major shift in the way the EDA industry addresses the complexity of nanometre design.

In nanometre technology, physical verification has become a sophisticated, multi-stage process that demands highly integrated approaches to the processing and handling of huge amounts of complex design data.

Total cycle time is on the rise due to more complex and larger designs, higher error counts and more verification iterations.

Calibre nmDRC responds to the need for reduced cycle time with a revolutionary new approach.

It provides four key capabilities that differentiate Calibre nmDRC substantially from traditional DRC tools.

Hyperscaling technology brings superior scalability and lightening fast run times for computationally intense applications.

Hyperscaling offers advanced data processing options that provide the fastest single CPU and multi-CPU performance to verify blocks in seconds and full chips in hours.

Hyperscaling reduces capital expenditures by extending the useful life of existing shared memory processor systems, and fully utilising inexpensive distributed rack systems.

Dynamic results visualisation and incremental DRC radically change the traditional sequential flow of the iteration process.

Dynamic results visualisation enables designers to begin debugging in seconds, as soon as the first error is identified in the initial verification run.

After errors are fixed, Incremental DRC conducts concurrent verification runs of the changed areas only.

This capability enables designers to perform multiple run/debug cycles in a single day, profoundly decreasing overall cycle time.

Integrated design for manufacturing (DFM) analysis and enhancement enable layout tradeoffs to minimise random, systematic and parametric yield loss.

Simultaneous DRC, yield analysis and layout modification decrease the total time required to produce a layout that is not only design rule compliant, but also high yielding.

Direct database access liberates designers to more easily use Calibre nmDRC throughout the flow, regardless of their choice of design creation environment.

Direct read of popular design and encapsulation databases (LEF/DEF, MilkyWay, OpenAccess, GDSII and Oasis) speeds DRC cycle time by eliminating the need for a separate data streamout process step.

Direct write enables back annotation of DFM enhancements into design databases.

Finally, support of the Oasis stream file format reduces file sise resulting in fast streamout and facilitating file transfer and data storage.

"We've seen outstanding results with the new Hyperscaling technology in Calibre nmDRC", said Kun-Cheng Wu, Design Development Director of Faraday Technology.

"With our current designs targeting at 90 and 130nm, compared with the original version, we found the new Hyperscaling performs more efficiently by speeding up DRC run times up to 5x".

"With the trend for bigger and more complex designs, it is critical to reduce physical verification run time, so we really appreciate Mentor's efforts in introducing the well-performed Hyperscaling in Calibre nmDRC".

"We're so excited about the Calibre nmDRC launch as it redefines the very nature of physical verification".

"The reception from customers during Calibre nmDRC's broad beta period has simply been 'wow'", said Joe Sawicki, Vice President and General Manager of the Design-to-Silicon Division at Mentor Graphics.

"While it is common wisdom in the industry that all innovation comes from the start-ups, Calibre is the rare exception to that rule".

"Calibre has defined innovation, first by delivering the only DFM tools integrated into a common platform with Calibre YieldAnalyzer, Calibre YieldEnhancer, and Calibre Litho Friendly Design tools, and now with Calibre nmDRC".

At 65nm, design signoff is no longer just DRC and layout versus schematic (LVS).

These basic components of physical verification are being augmented by an expansive set of yield analysis capabilities as well as layout enhancements, and printability and performance validation.

In addition, the increasing complexity of nanometre design rules reflects the fact that it is getting harder and harder to guide layout engineers, and their tools, to produce manufacturable layouts using traditional signoff approaches.

In the nanometre era, traditional compliance-based signoff, DRC/LVS and post-layout analysis using the as-drawn layout, does not produce designs with the desired yield.

To ensure high yields when using nanometre process technology, designers require new information and new levels of judgment that go beyond design rule checking to yield analysis.

They need new ways to assess the quality of their designs in light of the more complex process constraints and larger process variations they now face.

They need new ways to see the impact these constraints and variations have on the quality of their designs.

Finally, they need a new kind of work environment that allows them to understand which of these effects is the most important to address during the process of improving design quality.

Mentor's answer to this substantial change in the requirements for design signoff is the Calibre nm Platform.

To address the "new reality" of nanometre era designs, the Calibre nm Platform leverages next-generation technology in litho-friendly design (LFD), DRC, resolution enhancement technology(RET), and post-layout parasitic extraction and analysis to help design teams transition efficiently from a rule-based approach to a model-based approach where silicon accuracy and design cycle time is greatly improved.

"As the industry moves toward 65 and 45nm, the number and complexity of rules are exploding and a new approach to DRC is needed to ensure designs conform to manufacturing requirements in order to deliver acceptable yields", said Yee-Hwee Phuan, Director of Tapeout Operations at Chartered Semiconductor Manufacturing .

"There is an enormous increase in the number of details that must be considered prior to tapeout, and our experience with the Calibre nm Platform is that it takes salient issues into consideration, while making the tool user as efficient as possible".

At its core, the Calibre nm Platform delivers exceptional value due to intrinsic characteristics of the underlying architecture.

Calibre's fifth-generation data processing engine delivers best-in-class run time, and distributed processing enabling the use of low-cost Linux clusters.

Data processing engine, which is the heart of the Calibre nm Platform, ensures robust testing and implementation across all applications.

Common design platform integration enables rapid deployment of all the Calibre nm Platform applications into the user's design environment.

Integrated scripting environment across all application (SVRF and TVF) allow users to customise their design and verification environment to suite the specific and evolving needs of their design teams.

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