Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 21 July 2006
Reference flow 7.0 includes design for
test suite
Mentor Graphics' entire design for test tool suite is included in TSMC's Reference Flow 7.0.
Mentor Graphics Corporation and Taiwan Semiconductor Manufacturing Company (TSMC) have announced that Mentor Graphics' entire design for test (DFT) tool suite is included in the TSMC Reference Flow 7.0 YieldAssist joins TestKompress in the Reference Flow 7.0
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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As a result, designers now have a fully verified DFT flow from test generation through failure diagnosis based on Mentor Graphics' tools and methods.
Effective testing and failure diagnosis is crucial for designs manufactured with smaller geometries.
With the addition of YieldAssist to TSMC's Reference Flow 7.0, the Mentor DFT line-up provides an entire flow that offers effective scan testing, test pattern compression, memory built-in self-test (BIST), and failure diagnosis.
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TSMC provides a complete set of application notes and tutorials to facilitate DFT implementation.
"By including Mentor DFT tools in the Reference Flow 7.0, TSMC provides designers with a solid blueprint for high-quality testing and failure analysis," said Ed Wan, senior director of design service marketing at TSMC.
"Mentor's DFT technology provides designers with a flow to create high-quality products".
Yield issues and power management are key concerns at technology nodes below 90nm.
The combination of high-quality test and effective failure analysis are key to achieving yields.
TestKompress achieves high quality scan test by effective pattern compression with a wide variety of fault models, including at-speed faults, which are especially effective in achieving low defects per million (DPM) rates in nanometer designs.
YieldAssist perfectly complements TestKompress by enabling accurate failure diagnosis directly from compressed patterns, without the need for special diagnosis or "by-pass" patterns.
This means that failure diagnosis can be done directly on devices failing manufacturing test, without the need for retesting.
Defect site call-outs can be viewed in a physical realm by using an interface to Calibre RVE.
The modular TestKompress flow provides additional flexibility that can be used to minimise scan routing, reduce test pin-out requirements and manage power during testing.
"We have built upon our earlier relationship with TSMC to create a complete DFT and failure analysis flow," said Robert Hum, vice president and general manager of the Design Verification and Test division for Mentor Graphics.
"This has enabled us to offer DFT technology that meets real customer needs for nanometer designs".
"Such collabouration between the foundry and EDA tool vendor is essential for the smaller geometry designs".
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