Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Calibre OPCverify
Edited by the Electronicstalk Editorial
Team on 19 September 2006
Simulator ensures silicon-patterning
success
Matsushita has selected the Calibre OPCverify tool for use in production at 65nm and below.
Matsushita has selected the Calibre OPCverify tool for use in production at 65nm and below Calibre OPCverify addresses the challenge of managing the impact of "process variability" on yield by finding and fixing potentially catastrophic yield issues before manufacturing
This article was originally published on Electronicstalk on 10 Jan 2006 at 8.00am (UK)
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Process variability can have a dramatic effect on yield.
This is especially true in the lithographic process where variability puts image fidelity at risk even when the operating conditions of the lithographic system (lithographic process window) are acceptable.
To reduce the risk of silicon failure, avoid costly respins of both masks and silicon and safeguard time to market schedules, Calibre OPCverify detects lithographic errors or marginalities caused by process variability before the design goes to the mask or wafer manufacturer.
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Calibre OPCverify, which uses silicon-proven simulation models from Calibre OPCpro, is the next generation of RET verification, providing high simulation coverage of the entire chip to ensure silicon-patterning success.
The Calibre OPCverify pixel-based, dense simulation engine accounts for the effects of process variability using patented algorithms that define the conditions (dose, focus) that adversely impact pattern transfer.
All Calibre OPCverify modelling capabilities have been thoroughly characterised for the most advanced process conditions in production, including immersion lithography.
The rigorous model development and verification methodology used for the Calibre OPCverify tool allows it to satisfy the stringent requirements for both RET recipe validation and mask verification.
Another benefit of using Calibre OPCverify is that the tools take advantage of existing hardware in the most optimised way possible.
With the combination of high-speed computing power available on today's workstations, and the concurrent processing functionality in Calibre MTflex, very fast turn around times for full-chip RET verification can be achieved.
Because of the design-independent nature of the tool, users experience very predictable runtimes and excellent scalability.
While actual run time is dependent on the hardware used, the Calibre OPCverify terapixel simulator is scalable to hundreds of CPU's, can handle flat or hierarchical data, and ensures predictable turn around times in a production environment.
"Verification of post-OPC output is critical to minimising mask respins of million dollar mask sets, and avoiding time to market delays", said Hiroyuki Tsujikawa, Semiconductor Company, Matsushita Electric Industrial.
"Building on the Calibre platform for nanometre technologies has enabled Matsushita to develop a world-class process and gain a competitive advantage in delivering a wide range of system LSI".
"For 90nm and smaller technology nodes, the complexity of OPC and the constraints that go with it require verification to prevent silicon failures", said Joe Sawicki, Vice President and General Manager for the Design-to-Silicon Division at Mentor Graphics.
"Mentor is pleased to have Matsushita join the large and growing ranks of top semiconductor companies who have adopted our production proven verification platform".
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