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Design and Development Software
News Release from: Mentor Graphics UK | Subject: Calibre LFD
Edited by the Electronicstalk Editorial
Team on 31 May 2007
Infineon and Chartered use
litho-friendly design
Mentor Graphics has validated its Calibre LFD (litho-friendly design) results in silicon on 65nm process technology.
Mentor Graphics has validated its Calibre LFD (litho-friendly design) results in silicon on 65nm process technology A joint paper by Infineon Technologies and Chartered Semiconductor Manufacturing documents the positive results that can be achieved by implementing a lithographic process verification flow using Mentor Graphics' Calibre LFD
This article was originally published on Electronicstalk on 3 Apr 2006 at 8.00am (UK)
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Calibre LFD allows a design rule check (DRC) clean cell-based design to be analysed for manufacturability by simulating the effects of real-world lithographic process variations.
It is used early in design creation to identify lithography "hot spots" that can lead to a higher incidence of defects.
Calibre LFD uses production process models that provide the level of accuracy required to make modifications with confidence.
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Chartered has been collaborating with Mentor to provide an LFD production kit since March 2006.
The paper entitled "Hardware verification of litho-friendly design (LFD) methodologies [6521-20]" was presented in February 2007 at the SPIE Advanced Lithography Symposium and put together by a joint team from Infineon and Chartered (Reinhard Marz, Kai Peter, Sonja Grondahl, and Klaus Keiner of Infineon Technologies; and Byoung Il Choi, Shyue Fong Quek, Mei Chun Yeo, Nan Shu Chen, and Soo Muay Goh of Chartered).
The paper's conclusions are based on a series of experiments designed to prove the value of implementing LFD model-based physical verification in addition to traditional rule-based design when moving to 65nm and smaller geometries.
The experiments included lithography checks for minimum width (pinching), minimum space (bridging), minimum area overlap, and process variability index.
Physical measurements on real test wafers processed with controlled dose and focus parameter variations were found to correlate closely with the LFD simulations.
The experiments were run on an Infineon standard cell library manufactured in Chartered's Fab 7.
"It was important to prove the value of model-based lithography simulation capability by comparing simulated results to measurements of real test die produced on 65nm process", said Walter Ng, Senior Director of Platform Alliances at Chartered.
"This work using Infineon's standard cell library demonstrates that a highly accurate LFD flow for our 65nm process can provide substantial benefits for our customers".
The SPIE paper concludes that DRC compliance alone is not sufficient to avoid hot spots that can affect yield at 65nm and below.
The researchers also found that most hot spots could be attributed to a small number of cells.
This suggests that significant yield improvements can be obtained by modifying a relatively small number of layout hot spots when these are ranked by severity and yield impact.
"We are very gratified to see Infineon and Chartered leading the way to validate the LFD methodology", said Joe Sawicki, Vice President and General Manager, Design to Silicon Division, Mentor Graphics.
"We believe the results of this work should be of high interest to other companies who are currently evaluating the benefits of different DFM solutions, and are working on implementing an LFD-based verification flow".
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