Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 17 August 2007
Design companies agree on verification
The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability.
Cadence Design Systems and Mentor Graphics will standardise on a verification methodology based on the IEEEStd 1800-2005 SystemVerilog standard The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
Related stories
Mentor Graphics and UMC deliver IC design kits
Mentor Graphics and UMC have joined to deliver a complete turnkey design flow, including the availability of IC design kits, for UMC's RF and analogue/mixed-signal process technologies.
Mentor supports TI DSPs and MCUs
Mentor Graphics is the first to reach agreement with Texas Instruments to deliver coverification processor support packages (PSPs) for Texas Instruments DSP and microcontroller solutions.
It delivers on the promise of SystemVerilog with established interoperability mechanisms for verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows.
The OVM will include a robust class library and be available in source code format.
Cadence and Mentor have contributed both technology and resources to develop the foundation of the methodology and the libraries.
Further reading
Mentor and Xilinx have cores for communications
Mentor Graphics and Xilinx have released two high-level IP products to accelerate the design cycle of high-density FPGAs in communications applications.
Mentor upgrades wiring harness design suite
Mentor Graphics has upgraded its Capital H wire harness engineering software, used primarily by the automotive and aerospace industries.
Board timing analysis tool upgraded
Mentor Graphics and Altera have jointly announced support for the STAMP timing file format, allowing PLD and PCB designers to easily share PLD timing data for efficient board-level timing analysis.
The methodology will be made available under a standard open-source license, Apache License, Version 2.0.
"The OVM solves one of the biggest issues facing SystemVerilog adoption today", said Robert Hum, Vice President and General Manager of Mentor Graphics Design, Verification and Test Business Unit.
"Customers seek confidence that their investments in verification will be re-usable in the future".
"Having a methodology that works on a number of widely installed simulators and verification tools provides the confidence to move to SystemVerilog".
The OVM and supporting class library include the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments, and re-usable VIP in SystemVerilog.
The OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library.
The OVM will significantly shorten the time it takes to create verification environments, easily integrate verification IP and ensure code portability and re-use.
"With today's devices becoming more and more complex, engineers are under increasing pressure to speed deployment of verification methods", said Moshe Gavrielov, Executive Vice President and General Manager, Cadence Verification Division.
"With the OVM, Cadence and Mentor are delivering an efficient SystemVerilog-based tool-independent solution to help solve our combined customers' key design challenges".
"The industry as a whole will benefit with a much higher degree of interoperability, verification IP development and re-use, and ease of integration".
Unlike some alternatives, the OVM library will be open source, SystemVerilog IEEE-1800 compliant, and portable to any simulator supporting that IEEEstandard.
Under the terms of the Apache 2.0 license, it will also be easy for users and IP developers to re-ship the OVM code or derivatives and get support from multiple EDA vendors.
"The industry is clearly embracing SystemVerilog for functional verification, and this is further accelerated with an open source methodology that offers increased interoperability within the EDA ecosystem", said Sanjay Srivastava, President and CEO at Denali Software.
"Portability is key, and the OVM addresses this with multi-vendor support".
"The OVM and libraries are appealing to our broad verification IP customer base, and we will rapidly foster the transition to the OVM through our existing support for SystemVerilog and AVM".
"We've made a significant investment to develop a leading-edge SystemVerilog flow for our own design IP products, and will leverage the OVM to further enhance our SystemVerilog leadership".
"The OVM offers exactly what we have been looking for: a single open, robust, and interoperable verification methodology", said Predrag Markovic, President of HDL Design House in Beograd, Serbia".
""This greatly simplifies our development and support processes and will speed up the delivery of VIP and verification environment components to our customers".
"Customers will now benefit from plug-and-play verification IP".
"It's a win-win for everyone".
The OVM supports a mix of RTL and transaction-level abstractions for SystemVerilog and other high-level languages that support system-level design and verification.
The next generation of system-on-chip (SoC) design is already increasing customer demand in the area of transaction-level modelling and verification.
This growing demand will include the need to combine software-based simulation, hardware-based verification platforms, and established transaction-level interface standards.
"Doulos is committed to being the premier supplier of education for the OVM as the demands of complex SoC design strain alternate verification technologies", according to Robert Hurley, CEO Doulos.
"The commitment from Cadence and Mentor to offer an open verification methodology rooted on IEEE1800 with transaction-level modelling support that is interoperable amongst EDA tools and supports interoperable VIP will be matched by our commitment to support customers globally with training to allow them to get the most out of the OVM".
A preliminary release of the OVM is slated to be available for selected customers in Q3 2007.
A production release that includes the methodology and supporting library is scheduled to be available in Q4 of this year.
Additional functionality is planned for 2008.
Cadence and Mentor have collaborated to ensure that the OVM will run on their simulators, and will enable backwards compatibility with their existing environments: AVM from Mentor Graphics, and Incisive Plan-to-Closure Methodology (URM module) from Cadence.
• Mentor Graphics UK: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
