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Design and Development Software
News Release from: Mentor Graphics UK | Subject: Questa Codelink
Edited by the Electronicstalk Editorial
Team on 31 March 2008
Debug environment speeds ASIC validation
Isolating the cause of a failing processor driven test is a tedious and time consuming process, as RTL processor models delivered by the core vendor provide little or no debug visibility.
Mentor Graphics has released the Questa Codelink, an addition to the Questa Functional Verification Platform, designed to speed the validation of ASICs containing one or more embedded processors The Questa Codelink product is an integrated, source-level debug environment targeting processor driven tests
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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Isolating the cause of a failing processor driven test is a tedious and time consuming process, as RTL processor models delivered by the core vendor provide little or no debug visibility.
Mentor's Questa Codelink is a source-level debugger for RTL processor models supplied by ARM and MIPS.
Codelink shadows the RTL model and generates a debug dataset.
By presenting the user with a full view of software variables, call stack, registers and memory, test failures can be isolated in minutes rather than days or weeks.
With one third of all SoC designs moving to multicore in the next two years, it was important that Codelink support multicore debugging.
Tracking multiple code threads and observing message passing via shared memory are key elements in debugging synchronisation failures in multicore systems.
Codelink offers a variety of techniques for efficiently organising and viewing the many representations of relevant data associated with multicore source-level debug.
In addition, Codelink can log batch runs and interactively debug after simulation, eliminating the need to rerun long simulations in order to debug them.
Codelink replays a 15-hour simulation in three seconds.
Codelink also supports stepping backwards through source or assembly while variables, memory and registers views accurately reflect the state of the system.
"Over the past year our teaching customers, like InterDigital, have been instrumental in helping us to refine and enhance the Codelink product", said Serge Leef, General Manager of Mentor's System Level Engineering division.
"What has emerged is a highly efficient debug environment for MIPS and ARM-based SoCs".
"Codelink has proven to be a highly cost-effective and efficient tool for us, particularly the replay feature", said Kenneth Bartsch, Verification Lead at InterDigital.
"Prior to Codelink, certain bugs required multiple one-day re-simulations to fully diagnose".
"With Codelink replay we simulate just one time and isolate the failure (hardware or software) immediately".
"Both software and hardware engineers like the tool".
"Codelink was key to us taping out our new SlimChip SoC on schedule".
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