Chip design software stacks up 3D advantages
A novel design technique known as "through-Si via wafer stacking" offers a new dimension for chip designs.
Available now from Micro Magic, Max-3D is billed as the world's first true 3D-aware layout editor.
Max-3D can combine distinct process wafers, and allows the designer to view, edit and connect the independent wafers into one 3D stack chip.
This design technique - known as "through-Si via wafer stacking" - is a new dimension for chip designs.
It allows distinct wafers to be stacked on each other, and connected internally (see diagram).
This results in chips with denser designs and higher performance.
For example, a processor design in a 32nm technology could be combined with a 65nm memory and a 180nm analogue device - on the same 3D chip.
Furthermore, no changes need to be made to the foundry-supplied process development kits to incorporate these technologies in Max-3D.
It manages multiple levels and their respective tech files independently and collectively.
Max-3D is the only commercial layout editor capable of through-Si via 3D design.
It includes connectivity tracing, DRC checking and many other features found in Micro Magic's production-proven Max layout editor.
The product and its underlying technology have been in development for several years by one of the industry's leading experts - Dr Lisa McIlrath - Micro Magic's Chief Scientist.
"I was impressed that Max was able to provide the required speed and capacity required for these large complex 3D designs", says Dr McIlrath.
Through-Si via 3D wafer stack designs are an extreme challenge for design tools.
Current large 2D designs can crash many of today's layout editors.
A 3D chip that connects several levels of 2D layouts multiplies the complexity of the design.
Max-3D has demonstrated its capacity by displaying and editing a design of 1.2 trillion devices - in real time.
Like all Micro Magic products, Max-3D is fully programmable and customisable, and integrates well with other EDA tools.
Max-3D is available for a 30 day trial to qualified IC design organisations.
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