Product category:
Analogue and Mixed Signal ICs
News Release from: Zarlink Semiconductor | Subject: 0.6- and 0.35-micron libraries
Edited by the Electronicstalk Editorial
Team on 12 September 2001
Mixed-signal ASIC libraries up for grabs
Zarlink Semiconductor is offering free access to unique design libraries for 0.6- and 0.35-micron digital and mixed-signal processes at the company's foundry in Plymouth, England.
Zarlink Semiconductor is offering free access to unique design libraries for 0.6- and 0.35-micron digital and mixed-signal processes at the company's foundry in Plymouth, England The libraries include a comprehensive and proven range of component cells as well as tools to finalise chip designs, backed by a full range of design services available from the company
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
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"These libraries have been instrumental in building many of our own products and are of proven high quality", said Jim Tomkins, head, foundry design support team, Zarlink.
"By making them available to foundry customers, we are offering a means to dramatically improve their time-to-market of new products".
The libraries contain a comprehensive range of cells to enable full chip implementation.
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They include basic logic cells, a range of I/O cells with high ESD protection levels, and complex high performance PLLs, RAMs and ROMs.
All are fully supported by a range of chip construct leaf cells.
The libraries also support power and clock distribution and hierarchical layout strategies fundamental to any chip capability.
Zarlink is also offering free software support tools for memory selection and chip floorplan construction.
The memory generator helps optimise the memory architecture of a customer's product by guiding tradeoffs in performance, size and power consumption.
The base constructor contributes to the building of a complete chip by defining locations for all I/O cells from a few primary inputs while enabling interactive positioning of embedded complex cells.
As well, the software will insert all necessary "fill" cells and build a power distribution scheme by using chip construct leaf cells contained in the layout libraries to deliver a complete chip framework.
Zarlink's foundry design support team is also available to help customers accelerate or complete a chip design.
The team handles all aspects of the design process, from system specification through to tape-out, or can serve as consultants for various phases of product development.
"Zarlink's Plymouth facility is the first specialist fab to offer a complete in-house 0.35-micron library capability", said Tomkins.
"We offer a one-stop solution for customers with our comprehensive design support capability, comprised of cell libraries, process design kits and software tools for digital and mixed-signal processes".
Free access to design libraries and process design kits for the 0.6- and 0.35-micron mixed-signal processes manufactured at Zarlink's Plymouth foundry is available now.
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