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Product category: Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: SONET/SDH digital PLL
Edited by the Electronicstalk Editorial Team on 14 February 2002

Three PLLs in one for SONET
synchronisation

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Zarlink Semiconductor has the world's first commercial digital PLL chip that fully meets rigorous international standards for very high performance synchronisation in SONET/SDH systems.

Zarlink Semiconductor has the world's first commercial digital PLL chip that fully meets rigorous international standards for very high performance synchronisation in SONET/SDH systems Zarlink's newest PLL is based on a novel, patent-pending architecture that incorporates three independent PLLs within a single chip

This innovative approach enables the device to reduce signal wander - a cyclical variation in signal frequency that is a prime cause of data errors in optical communications networks - to levels stipulated by international standards.

As a result, the chip is the industry's first off-the-shelf SONET/SDH digital PLL to fully meet the exacting synchronisation requirements of Telcordia's GR-1244-CORE and GR-253-CORE standards for SONET Stratum 3E clocks, and the ITU's G.812 requirements for SDH Type I clocks.

The device begins sampling in March 2002 and is the second in Zarlink's family of high performance SONET/SDH digital PLLs.

"By designing a highly flexible digital PLL that meets global synchronisation requirements for optical networking equipment, we're saving our customers design cycle time and money", said Michael Rupert, product line manager, Zarlink Semiconductor.

"Networking companies now have the choice of using our commercial timing chip for SONET Stratum 3E and SDH Type I clocks, rather than designing their own clocks or buying more costly timing modules".

Zarlink's new device is a network element PLL that provides synchronisation in SONET and SDH systems.

The chip can be used on timing cards and line cards in SONET/SDH add/drop multiplexers and uplinks, terminal multiplexers, integrated access devices, and ATM (asynchronous transfer mode) edge switches.

With its ground-breaking chip architecture, Zarlink has met the key technical challenges in designing a digital PLL for SONET Stratum 3E and SDH Type I clocks - controlling signal wander and timing transients, and providing holdover accuracy.

For example, the device's holdover accuracy of 0.1ppb (parts per billion) permits network equipment to continue to transmit and receive data with a high degree of accuracy, even when the source of network synchronisation is disrupted or changed.

Zarlink's PLL is highly flexible and meets a wide range of synchronisation requirements, including Telcordia's GR-1244-CORE for Stratum 3E and 3 clocks and GR-253-CORE standard for SONET Stratum 3E, 3, and SONET minimum clocks.

For SDH equipment clocks, the device meets the ITU-T's G.812 standard for Type I clocks, and G.813 for Option 1 and Option 2 clocks.

The chip also provides multiple clocks for legacy PDH (plesiochronous digital hierarchy) equipment, and generates timing for CompactPCI, ST-BUS and GCI backplanes.

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