SAR chips take SRAM and PLLs onboard

Available now from Zarlink Semiconductor are the industry's two most highly integrated AAL1 segmentation and reassembly chips for TDM-to-ATM conversion.

Available now from Zarlink Semiconductor are the industry's two most highly integrated AAL1 SAR (segmentation and reassembly) chips for TDM-to-ATM (time-division multiplex-to-asynchronous transfer mode) conversion.

By eliminating the need for up to six external devices in TDM-to-ATM designs, Zarlink's new MT90528 and MT90520 AAL1 SARs significantly reduce board space, lower system costs, and boost efficiency.

The 28-port MT90528 and the 8-port MT90520 are the industry's first TDM-to-ATM conversion devices with on-chip, per-port PLLs for network synchronisation, plus on-chip SRAM for channel buffering.

The chips also achieve low voice processing delay (latency), eliminating the need for external VECs (voice echo cancellers).

These features, combined with support for multiple data transfer modes, make Zarlink's new AAL1 SARs the industry's most flexible, integrated, and cost-effective devices for TDM-to-ATM interworking.

The MT90528 and the MT90520 are designed for applications in ATM edge switches, multiservice switches, broadband digital loop carriers, and ATM voice and media gateways.

The lower-density MT90520 is also suitable for use in integrated access devices.

"Customers want to optimise their TDM-to-ATM conversion designs for performance and cost-efficiency, while using less board space", said Bruce Ernhofer, product manager, Zarlink Semiconductor.

"Our two new AAL1 SARs deliver low-latency performance and a level of integration that reduces the need for external framers, echo cancellers, and memory devices".

Zarlink's MT90528 and MT90520 receive CBR (constant bit rate) traffic from DS1/E1 TDM ports operating at 1.544/2.048Mbit/s and convert it to 53byte cells for transport over ATM networks.

The MT90528 handles 28 DS1/E1 ports; the MT90520 supports eight ports.

The chips deliver unmatched performance when operating in the industry's most common mode of TDM-to-ATM data transfer, known as UDT (unstructured data transfer), also called unstructured CES (circuit emulation services).

UDT switches all data arriving at a given input across a single VC (virtual circuit), making it ideal for applications like wide-area PBX (private branch exchange) interconnect, where high volumes of data are exchanged between two fixed points.

To enhance UDT performance, Zarlink equipped each input on the devices with a digital PLL, enabling network synchronisation to be performed on-chip, an industry first for AAL1 conversion devices.

The PLLs allow each input to be synchronised to a different network clock, eliminating the need for up to four external framers.

To further optimise operation in UDT mode, the MT90528 and MT90520 feature on-chip SRAM.

The SRAM enables cell payloads assembled in UDT operation to be buffered on-chip, eliminating the need for external memory.

In addition to UDT, each TDM input on Zarlink's new chips can be programmed to support two other data transfer modes: structured CES, and structured CES with CAS (channel associated signaling).

This flexible port assignment scheme allows multiple TDM-to-ATM service requirements to be met within a single design.

Operation in all modes conforms to CES standards defined by the ITU-T, and the ATM Forum (AF-VTDA-0078/0089/0085).

The MT90528 and MT90520 also enable higher performance by introducing only 500us of process latency to TDM-to-ATM conversion designs.

This low and predictable latency reduces or eliminates the requirement for external VECs, which are needed to clean up the echo tails often caused by longer voice processing delays.

In structured CES modes, the chips support N x 64Kbit/s service over up to 896 bidirectional VCs, with up to 128 TDM channels per VC.

The ATM interfaces on Zarlink's new devices are Level 2 Utopia ports.

The devices operate as either Utopia "masters" or "slaves" in Utopia Level 1 mode, and transfer 8 or 16bit data at clock rates up to 52MHz.

The ATM ports also act as multi-PHY (physical layer) in Level 2 mode.

Zarlink's new AAL1 SAR devices are now in volume production.

The devices are offered in pin-to-pin compatible 456-ball PBGA (plastic ball grid array) packages and supported by reference designs and API software.

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