Packet processors put TDM on Ethernet

A new class of communications chips promises to significantly redefine the economics of delivering TDM voice and data over standard IP and Ethernet packet networks.

A new class of communications chips will significantly redefine the economics of delivering TDM voice and data, the most widely deployed access services in the world, over standard IP and Ethernet packet networks.

Zarlink's MT90880/1/2/3 packet processors are the industry's first devices to achieve high-density CESoP (circuit emulation services over packet) for TDM.

With this capability, low-cost IP/Ethernet networks can - for the first time - transport high volumes of profitable TDM access services, such as T1/E1 leased lines, with the same high quality as more expensive TDM networks.

The new devices are also the first purpose-built packet processors to support scaleable, low-cost Ethernet backplanes, which are poised to replace more costly, congestion-prone TDM backplanes.

A single Zarlink packet processor supports 32 T1/E1 ports, offering up to six times the density of TDM-to-IP products based on software-intensive microprocessors.

Zarlink's devices also boost service quality by building packets up to 16 times faster than microprocessors, and are much more cost-effective.

One 32-port packet processor costs about 50% less than equivalent-density microprocessor solutions.

"No other device on the market comes close to the performance of our hardwired packet processors", said Jeremy Lewis, product line marketing manager, Zarlink Semiconductor.

"These high-grade packet engines are in a class all their own".

Several global customers have already qualified Zarlink's packet processors for access equipment that delivers high-density TDM CESoP.

This equipment will allow operators to route T1/E1 traffic across low-cost Ethernet MANs or WANs (metropolitan- or wide-area networks), thus eliminating costly TDM trunks while extending investments in installed TDM access infrastructure.

Customers are also evaluating Zarlink's chips for access equipment that will solve bottlenecks by replacing legacy TDM backplanes with backplanes based on Ethernet switches.

Growth in TDM access traffic is causing congestion on TDM backplanes, or crosspoint switches, which are difficult and expensive to scale.

Zarlink's packet processors pave the way for lower-cost Ethernet backplanes that allow next-generation access equipment to easily and cost-effectively scale beyond OC-12 rates.

Zarlink's MT90880/1/2/3 packet processors set up, synchronise, time, and manage TDM-over-packet connections from end-to-end, enabling low-cost IP/Ethernet networks to achieve carrier-class, TDM-like service quality.

The packet processors incorporate 12 patent-pending technologies related to the mapping, signalling, and buffering of TDM circuits over packet networks.

These techniques help the chips overcome complex timing and synchronisation issues that, until now, have prevented the reliable, consistent delivery of carrier-grade, constant-bitrate voice services over variable-bitrate packet networks.

The ability of Zarlink's new packet processors to synchronise to TDM networks is also improved by on-chip, digital PLL (phase-locked loop) circuitry that meets the requirements of Telcordia's GR-1244-CORE standard for Stratum 4E clocks.

Voice quality on packet networks is negatively affected by latency, a measure of end-to-end delay.

The MT90880/1/2/3 improve service quality and ease timing budgets by achieving low and stable packet processing latencies of less than 125us, regardless of channel density.

By contrast, microprocessor solutions introduce latencies of up to 2ms - 16 times longer than Zarlink's chips - and their latencies vary widely, depending on the number of channels being processed.

The MT90881 and MT90883 are designed for CESoP applications in next-generation access equipment such as gigabit Ethernet service routers and broadband aggregation platforms.

The MT90881 converts up to 32 T1/E1 streams, or 1024 TDM channels, in Nx64Kbit/s configurations to Ethernet/IP packets.

The MT90883 converts eight T1/E1 streams or 256 channels.

The MT90880 and MT90882 are tailored for TDM backplane replacement in telephone switches, multi-service access platforms, and voice-over-IP gateways.

To support these and other applications, such as offloading TDM data services to remote access concentrators, the devices feature onboard nonblocking TDM switches.

The switches route incoming traffic either directly to packetisation circuitry, or through a local TDM interface to resource pools.

The MT90880 incorporates a 1024 x 1024-channel switch that supports 32 streams of Nx64Kbit/s TDM traffic.

The MT90882 has a 256 x 256-channel switch that supports eight streams of Nx64Kbit/s traffic.

The TDM interfaces on all four chips accept traffic at rates of 2.048 or 8.192Mbit/s.

The packet switch interfaces are dual redundant MIIs (media independent interfaces) operating at 100Mbit/s.

The four chips are also pin-to-pin compatible, allowing designers to use the same architecture for both low- and high-density access equipment.

Zarlink's MT90880/1/2/3 chips are now in volume production.

The devices are designed into 0.18 micron CMOS (complementary metal oxide silicon) technology and offered in 456-pin PBGA (plastic ball grid array) packages with dimensions of 27 x 27mm.

The processors are supported by comprehensive TDM-to-packet reference designs, evaluation boards, APIs (application programming interfaces), and application-level software.

(This was Electronicstalk's Top Story on 11 October 2002).

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