Digital PLL meets Sonet synchronisation specs

A new fully featured, high-speed digital timing chip allows equipment designers to quickly and cost-effectively meet Sonet/SDH network synchronisation requirements.

A new fully featured, high-speed digital timing chip allows equipment designers to quickly and cost-effectively meet Sonet/SDH network synchronisation requirements.

To avoid network errors, Sonet/SDH standards stipulate that all system elements, including a diverse range of access and metro equipment, comply with stringent specifications for network timing and synchronisation.

As a result, Sonet/SDH equipment must be equipped with timing circuitry capable of generating carefully controlled output clocks.

Zarlink's ZL30407 digital PLL chip delivers an extensive set of output clocks and reliability features that simplify, shrink, and lower the cost of standards-compliant timing circuits for access and metro equipment.

The device complies fully with Telcordia's GR-1244 and GR-253 standards for Sonet minimum and Stratum 3 clocks, and the ITU's G.813 Option 1 and 2 for SDH clocks.

In holdover mode, the ZL30407 meets the exacting demands of Stratum 3E and G.812.

Zarlink's new digital PLL features a 155.52MHz output clock with very low jitter.

Jitter, a short-term variation in clock timing, can cause data errors in optical networks.

The worst-case jitter of the ZL30407 clock is only 325ps.

This high stability level allows the clock to link directly to OC-3/STM-1 interface chips without first being "cleaned" of jitter by external analogue PLLs.

"We're saving designers time, money, and board space by driving complexity out of timing circuitry", said Michael Rupert, Marketing Manager, Timing and Synchronisation, Zarlink Semiconductor.

"Timing circuits based on our chip are easier to build than in-house designs and help designers achieve faster time-to-market".

Several global equipment vendors are now evaluating Zarlink's ZL30407 device for use on timing cards in digital subscriber line access multiplexers, wireless infrastructure, digital loop carriers and gateways.

The device is also suitable for PDH systems, and networking equipment with ST-BUS, GCI, or H.110 backplanes.

Zarlink's ZL30407 digital PLL, by generating 10 different output clocks, supports a range of different framers, switches, mappers, and line interface chips.

The high-speed 155.52MHz LVDS clock complements outputs operating at 1.544, 2.048, 4.096, 6.312, 8.192, 16.348, 19.44, 34.368 and 44.736MHz.

In addition, the chip produces three 8kHz STbus framing pulses.

The inputs on the ZL30407 chip are flexible.

The PLL accepts frequency references from two independent sources, and synchronises to any combination of 8kHz, 1.544MHz, 2.048MHz or 19.44MHz.

The ZL30407 PLL has high-performance reliability features that enhance system integrity and ensure compliance with Sonet/SDH standards.

The two input reference signals are continuously monitored.

If the primary reference drifts by more than 12ppm from its preset frequency, the device immediately raises an alarm.

This gives the system processor the forewarning needed to switch the ZL30407 PLL to its secondary reference before there is any perceptible impact on its output clocks.

If both input references become corrupted, the chip seamlessly transfers into holdover mode.

In holdover, the device generates a reference clock that is accurate to within 10e-12, meeting the requirements of Stratum 3E.

This clock remains stable for 30 times longer than Stratum 3 holdover clocks.

Technicians thus have time to service equipment without undue interruption to subscriber services.

The ZL30407 PLL is now in production.

The device is offered in an 80-pin LQFP package measuring 14 x 14mm.

In quantities of 1000 the chip is priced at US $67.00.

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