Analogue PLL features six clocks

Zarlink Semiconductor has launched an analogue timing chip with six low-jitter output clocks - more than any other competing product - for optical line cards.

Zarlink Semiconductor has launched an analogue timing chip with six low-jitter output clocks - more than any other competing product - for optical line cards.

With Zarlink's highly integrated ZL30406 analogue PLL (phase locked loop), designers can shrink the size, cost, and power of line card timing designs.

"Zarlink's ZL30406 device sets a new benchmark for integration, flexibility and performance in analogue PLLs", said Louise Gaulin, Product Line Director, Timing and Synchronisation, Zarlink Semiconductor.

"Coupled with the recent launches of our ZL30407 digital PLL for timing cards, and ZL30462 timing module for line cards, Zarlink is now the only company with a comprehensive range of analogue, digital, and module timing and synchronisation products".

Analogue PLL devices perform critical timing and synchronisation functions in communications equipment, including line cards used in Sonet/SDH access and metro equipment.

Zarlink's ZL30406 analogue PLL regenerates and multiplies clock signals - or reference frequencies - to higher frequencies, while also "cleaning up" jitter.

"The ZL30406 device is the first Sonet/SDH analogue PLL to generate six low-jitter output clocks - the widest range of clocks in its class", said Darren Ladouceur, Marketing Manager, Timing and Synchronisation, Zarlink Semiconductor.

"The jitter performance of the device surpasses OC-48 and STM-16 requirements".

The ZL30406 chip delivers: four differential LVPECL clocks at 77.76 MHz; a differential current mode logic clock programmable to 19.44, 38.88, 77.76 or 155.52MHz; and a single-ended CMOS clock at 19.44MHz.

The four differential LVPECL clock outputs interface directly to other devices on Sonet/SDH line cards, including framers, mappers, and serdes chips, reducing or eliminating the need for external glue logic circuitry.

Glue logic - typically a range of fan-out and logic translation devices - adds cost, consumes power, and increases design footprints.

Along with the flexibility to select from different frequencies and logic formats, designers can enable or disable ZL30406 clocks as required, giving them a high degree of control.

The ZL30406 chip delivers ultralow jitter performance of 0.46ps RMS.

This performance exceeds Telcordia's GR-253-CORE jitter requirements for OC-3 to OC-48 optical rates, and the ITU-T's G.813 Option 1 and 2 requirements for STM-1 to STM-16 rates.

The ZL30406 device can be used on its own, or in combination with one of Zarlink's digital PLLs, such as the MT9046 or ZL30407 chip, to provide an integrated, highly featured timing system with guaranteed performance.

The ZL30406 analogue PLL is now in production.

The device is offered in a 64-pin TQFP measuring 10 x 10mm.

In quantities of 1000, the device is priced at US $44.15.

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