Product category:
Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: ZL30410
Edited by the Electronicstalk Editorial
Team on 05 August 2003
Digital PLL banishes jitter
The ZL30410 digital PLL is a full-featured timing chip with the industry's lowest jitter, for access line cards operating at OC-3 rates.
The ZL30410 digital PLL is a full-featured timing chip with the industry's lowest jitter, for access line cards operating at OC-3 rates With the ZL30410 digital PLL and the company's analogue PLLs for line cards, Zarlink is the first semiconductor company to offer both digital and analogue timing devices for standards-compliant line cards in high-speed Sonet/SDH access systems
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
Related stories
Packet processor for broadband networks
Mitel Semiconductor has introduced the world's highest density AAL2 segmentation and re-assembly (SAR) device.
Quality of service is key to Gigabit Ethernet ICs
The MVTX2800 family of Gigabit Ethernet switching ICs from Zarlink Semiconductor deliver full-wire speed forwarding and leading quality of service features to metropolitan optical access equipment.
Zarlink's ZL30410 timing chip generates and synchronises clock signals used by other line card devices, such as OC-3/STM-1 framers, mappers, switches and optical line interface chips.
The company's analogue PLLs connect seamlessly to the ZL30410, and support higher-speed applications by producing clock signals for OC-12/STM-4 or OC-48/STM-16 framers.
"To handle rising traffic volumes at the network edge, access systems must operate at higher speeds, and that makes their timing circuitry more complex", said Michael Rupert, Marketing Manager, Timing and Synchronisation, Zarlink Semiconductor.
Further reading
Chipset saves space, cuts costs for TDMA handsets
Zarlink Semiconductor has announced a new highly integrated RF chipset for cellular handsets operating in dual-mode TDMA/AMPS networks.
First AAL1 device to perform on-chip ATM switching
Zarlink Semiconductor claims the MT90503 is the industry's highest density AAL1 segmentation and reassembly (SAR) chip for TDM to ATM conversion.
Ultra-low-power process aims for low-voltage SoCs
Zarlink Semiconductor has expanded its foundry services with a new ultra-low-power analogue nonvolatile 0.35-micron CMOS process optimised for low-voltage (1V) and low-power applications.
"Our digital and analogue line card PLLs are fully tested for interoperability, which reduces complexity and makes it easier for designers to comply with stringent Sonet/SDH network timing standards".
Several global equipment vendors are evaluating Zarlink's line card chips for use in routers, multiservice access devices, DSLAMs, gateways and next-generation DLCs.
The jitter performance of Zarlink's new ZL30410 chip is best in class, with ratings 30% lower than comparable digital PLLs.
Jitter, a cyclical variation in signal frequency, causes data errors in optical networks.
The superior performance of Zarlink's chip means it can generate - without external components - the 155.52MHz clocks that drive OC-3/STM-1 access uplinks, and the 16.384MHz clocks that drive jitter-sensitive TDM digital switches.
By contrast, clocks at these frequencies produced by digital line card chips from other vendors must be "cleaned" of jitter by external analogue PLLs.
In addition to clocks for OC-3/STM-1 links, Zarlink's ZL30410 chip generates all other clocks typically used in high-speed access line cards, including a 19.44MHz clock, and clocks for services delivered over ST-bus, DS1/E1, DS2, and DS3/E3.
On its inputs, the ZL30410 accepts two reference clocks.
It detects the frequency of both clocks and synchronises to any combination of 8kHz, 1.544MHz, 2.048MHz and 19.44MHz.
The ZL30410 chip offers "hitless" reference switching, a feature that enhances reliability and eases maintenance procedures.
The device continuously monitors both input references.
If the active reference is interrupted, the chip switches instantly to holdover mode, generating its own reference clock based on data collected from past reference signals.
This gives the system time to react to the problem, and if required, switch the ZL30410 chip to its other input reference signal without disturbing its output clocks.
Zarlink's ZL30410 device complies with Telcordia's GR-253-Core for OC-3 jitter generation, and the ITU's (International Telecommunication Union-Telecommunications) G.813 Option 1 for STM-1 jitter generation.
It is also compatible with GR-253-Core Sonet Stratum 3 clocks and G.813 slave equipment clocks.
The ZL30410 digital PLL is in production.
The device is offered in an 80-pin LQFP measuring 14 x 14mm.
In quantities of 1000, the chip is priced at US $22.50 each.
• Zarlink Semiconductor: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
