Product category:
Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: ZL30414
Edited by the Electronicstalk Editorial
Team on 12 August 2003
PLL's six clocks simplfy line card
design
Zarlink Semiconductor has a new high-performance analogue PLL timing chip for optical line cards operating at up to OC-192 rates.
Zarlink Semiconductor has a new high-performance analogue PLL timing chip for optical line cards operating at up to OC-192 rates With six output clocks - more than any competing product - and jitter performance that surpasses industry specifications, the ZL30414 device simplifies line card design and lowers space requirements
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
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Analogue PLLs perform timing and synchronisation functions in communications equipment, including Sonet/SDH line cards in network core, metro, edge and access equipment.
Zarlink's flexible ZL30414 analogue PLL accepts one clock signal and simultaneously outputs six low-jitter, higher-frequency clocks.
"At OC-192 rates, jitter performance is a leading design parameter", said Darren Ladouceur, Marketing Manager, Timing and Synchronisation, Zarlink Semiconductor.
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"Our ZL30414 device beats industry jitter specifications, and by providing six output clocks at three different frequencies, delivers cost and footprint improvements".
With the ZL30414 device and the ZL30406 chip - introduced in May 2003 - Zarlink now offers analogue PLLs for Sonet/SDH line cards operating at rates from OC-3/STM-1 to OC-192/STM-64.
Zarlink is the only company in the industry with a comprehensive range of analogue, digital and module timing devices, and now offers reference designs that help customers determine their requirements and implement system-level timing and synchronisation solutions.
Jitter is a short-term variation in clock timing caused by noise from various sources, such as power supplies, and thermal noise form other components.
Noise can broaden the clock signal, making it difficult for the receiving equipment to discern the original signal, which can in turn cause data errors.
Ultra-low jitter, measured in picoseconds, is crucial in systems operating at high speeds.
For OC-192/STM-64 systems operating at 10Gbit/s, the jitter budget - the amount of timing variation allowed from various sources - is extremely small, making the performance of timing devices critical.
The jitter performance of the ZL30414 analogue PLL easily meets Telcordia and ITU-T requirements for OC-192/STM-64 systems.
The chip's jitter performance is 0.52ps RMS, providing significant margin against Telcordia's GR-253-Core requirement of 1ps RMS.
As well, the ZL30414 device delivers a maximum peak-to-peak jitter performance of 6.95ps, surpassing ITU-T G.813 Option 1 and 2 requirements for a maximum peak-to-peak jitter performance of 10ps for STM-64 rates.
The ZL30414 device accepts one input reference clock at 19.44MHz and provides six output clocks: four differential LVPECL clocks at 622.08MHz - the most common frequency for OC-192/STM-64 devices; a differential CML clock at 155.52MHz; and a 19.44MHz CMOS clock.
The four LVPECL clocks interface directly to such line card devices as framers, mappers and serdes (serialiser/deserialiser) chips.
By providing the logic level required by these devices, the ZL30414 analogue PLL eliminates the need for glue logic - typically fan-out and logic conversion chips - which is required when using most competing products.
Glue logic leads to a more complex design, consumes power, increases design footprint and cost, and adds to the jitter budget.
The ZL30414 device is in volume production.
The chip is offered in a 64-pin TQFP (thin quad flat pack) measuring 10 x 10mm.
In quantities of 1000, the ZL30414 is priced at US $55.84.
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