Product category:
Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: ZL50111 family
Edited by the Electronicstalk Editorial
Team on 23 September 2003
Zarlink announces advanced CESoP
processors
The Zarlink ZL50111 packet processors are an enabling technology for the adoption of IP/Ethernet technology in metro networks
Zarlink's ZL50111 series are being launched as the first packet processors which can send high TDM traffic volumes over IP/Ethernet networks with equivalent voice quality and service flexibility as conventional, TDM-based telephone networks Up to 32 T1/E1 streams can be handled
This article was originally published on Electronicstalk on 30 Apr 2004 at 8.00am (UK)
Related stories
Packet processors meet latest TDM specs
The ZL50111 family of TDM-over-IP packet processors are the first devices to meet the protocols outlined in the industry's newest recommendation for TDM circuit transmission over packet networks.
Packet processors unite US and Korean designs
Four equipment manufacturers in the USA and Korea are developing a range of networking equipment based on the ZL50111 family of TDM-over-IP packet processors.
The three-chip ZL50111 series is standards-compliant and allows TDM-to-IP/Ethernet access systems to have improved performance and reduced cost, size, and power consumption too.
Thanks to the rising volumes of IP data traffic, service providers are stepping up investments in metro Ethernet packet networks, which often feature high-speed IP/Ethernet links to customer sites.
Consequently, there's growing demand for a new class of network edge equipment with TDM-to-IP/Ethernet conversion capabilities, or CESoP, which lowers costs by allowing less expensive Ethernet networks to carry high-quality, profitable TDM services, such as T1/E1 leased lines.
Further reading
Processors package up to four circuits
Following the launch of three low-density CES-over-packet processors, Zarlink Semiconductor now offers the industry's only end-to-end portfolio of circuit-to-packet devices.
Packet processor for broadband networks
Mitel Semiconductor has introduced the world's highest density AAL2 segmentation and re-assembly (SAR) device.
Quality of service is key to Gigabit Ethernet ICs
The MVTX2800 family of Gigabit Ethernet switching ICs from Zarlink Semiconductor deliver full-wire speed forwarding and leading quality of service features to metropolitan optical access equipment.
As an "enabling technology" for the adoption of IP/Ethernet technology in metro networks, major global equipment vendors are already designing the new processors into equipment such as routers, switches, integrated access devices, wireless backhaul systems, and Ethernet passive optical network systems.
One challenge in delivering CESoP is to get the precise levels of network synchronisation and clocking to deliver constant-bitrate voice traffic over variable-bitrate packet networks reliably.
Zarlink has achieved this with over 15 patent-pending hardware and software processing techniques allowing the ZL50111 family to deliver carrier-class voice quality in both adaptive and differential synchronisation modes.
Voice quality has also been enhanced by on-chip QoS mechanisms like weighted fair queuing and strict priority, to reduce the effects of network latency, or end-to-end packet transit time, by giving time-sensitive voice packets priority over data packets in processing queues.
Jitesh Vadhia, the Senior Vice President and General Manager, Network Communications at Zarlink Semiconductor says: "Our second-generation packet processors deliver the industry's most advanced and cost-effective method of circuit-to-packet conversion and transmission - an emerging capability known as Circuit Emulation Services over Packet, or CESoP.
"The key to this achievement is the first-ever integration of two critical voice/data convergence functions - network timing and synchronisation, and packet processing - in a single device".
Bruce Ernhofer, Product Manager, Packet Processors, at Zarlink adds: "Our devices use innovative processing algorithms to perform complex TDM clock recovery functions on-chip - a world first.
"This capability, combined with priority queuing, allows the chips to consistently meet the industry's stringent QoS criteria for voice transport".
The TDM-to-IP/Ethernet packet processor range consists of three chips allowing equipment manufacturers to support a wide range of TDM traffic densities and data rates cost-effectively.
CESoP chips from other vendors support only one T1/E1 port, but the ZL50111 provides CESoP for 32 T1/E1 ports, or 1024 x 64Kbit/s channels, and two of the ports can be configured to deliver high-speed T3/E3 services operating at 45Mbit/s.
The ZL50110 processes eight T1/E1 ports, or 256 x 64Kbit/s channels, and the ZL50114 supports four T1/E1 ports, or 128 channels.
All three chips support a broad array of TDM traffic formats, including unstructured mode, structured mode, and fractional N x 64Kbit/s mode.
All the TDM ports are equipped with their own DCO (digitally controlled oscillator) for improved service flexibility, enabling each port to be synchronised to a reference clock, which in turn lets services be routed on a per-port basis.
For example, traffic on some TDM ports might be sent via Ethernet to the PSTN (public switched telephone network), while services on other ports can be Ethernet-routed to different locations, bypassing the PSTN.
This is done without using external memory devices.
The packet processor range features on-chip SRAM circuitry with enough capacity to buffer data in 32 T1/E1 ports for 16ms, more than enough for most metro Ethernet networks, which normally have latencies, or end-to-end data transport times, of 5ms or less.
The chips meet the ITU-T's G.823 and G.824 traffic interface specifications for jitter and wander control in T1/E1 networks.
Thay also meet draft standards for native TDM circuit emulation proposed by the Internet Engineering Task Force's PWE3 working group.
The ZL50111 range is already in production, and there's a complete reference design, an evaluation board and a software API to support them.
All are offered in 552-pin PBGA packages.
For 1000 unit orders, the ZL50111 costs US$276.47, the ZL50110 US$181.18, and the ZL50114 US$129.41.
(Updated by CR, May 2007).
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