Product category:
Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: ZL30415
Edited by the Electronicstalk Editorial
Team on 01 December 2003
Analogue PLL claims best fit for line
cards
A new analogue timing chip is claimed to deliver the industry's best combination of performance and features for Sonet/SDH line cards operating at up to OC-12/STM-4 rates.
A new analogue timing chip is claimed to deliver the industry's best combination of performance and features for Sonet/SDH line cards operating at up to OC-12/STM-4 rates The ZL30415 analogue PLL is an integrated timing device that offers jitter performance surpassing industry requirements and a frequency-selectable output clock that reduces design costs
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
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Most timing chips do not match the ZL30415 device for value, delivering marginal jitter performance or lacking the features necessary to meet OC-12 requirements.
"With the ZL30415 analogue PLL, we're meeting the most critical design requirements for OC-3 to OC-12 applications - jitter performance and flexibility", said Darren Ladouceur, Marketing Manager, Timing and Synchronisation, Zarlink Semiconductor.
The ZL30415 timing chip provides ultra-low jitter performance of a maximum of 3.3ps RMS for OC-3/STM-1 rates, and 3.5ps RMS for OC-12/STM-4 applications.
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This performance surpasses Telcordia's GR-253-CORE requirements for OC-3 to OC-12 optical rates, and the ITU-T's G.813 Option 1 and 2 specifications for STM-1 to STM-4.
Zarlink's analogue PLL is one of the few available devices meeting the more stringent jitter limits imposed by framers and other interfacing devices.
Offering analogue, digital and module timing devices, coupled with reference designs and engineering support, Zarlink is the only company with end-to-end timing and synchronisation products for Sonet/SDH equipment.
Analogue PLLs perform timing and network synchronisation functions in line cards, regenerating and multiplying clock signals to higher frequencies, and cleaning up jitter, a short-term variation in clock timing that causes data errors in optical equipment.
The ZL30415 timing chip provides two output clocks - one fixed 19.44MHz CMOS clock, and a frequency- selectable LVPECL (low voltage positive emitter coupled logic) clock.
Designers may select any of the standard frequencies used in OC-3/STM-1 to OC-12/STM-4 applications: 19.44, 38.88, 77.76, 155.52 or 622.08MHz.
The frequency-selectable output clock simplifies the design of OC-3/OC-12 line cards.
For example, designers using the ZL30415 device in a system with both OC-3 and OC-12 line cards requiring different LVPECL clock outputs can simply "cut and paste" the design from one line card to the other, changing only the programmable output frequency required for the given application.
The LVPECL clock output interfaces directly with other devices on Sonet/SDH line cards, such as framers, mappers, and serdes chips, thus eliminating the need for external translation circuitry that adds cost, consumes power and increases the design footprint.
The ZL30415 device can be used on its own to address timing requirements for line cards operating at up to OC-12/STM-4 rates, or in combination with Zarlink digital PLLs such as the MT9046 or ZL30410 devices, in highly featured timing systems.
The ZL30415 timing chip enhances Zarlink's portfolio of analogue PLLs with different features to meet synchronisation and jitter requirements for Sonet/SDH line cards in network core, metro, edge and access equipment operating at OC-3/STM-1 to OC-192/STM-64 rates.
The ZL30415 analogue PLL is in volume production.
The chip is offered in a 64-ball CBGA (chip ball grid array) measuring 8 x 8mm.
In quantities of 1000, the ZL30415 device is priced at US $24.
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