Product category:
Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: ZL30100/1
Edited by the Electronicstalk Editorial
Team on 06 April 2004
Digital PLLs deliver superior jitter
performance
Two new digital PLLs claim industry-leading jitter performance and superior features to ensure the reliable transport of data, multimedia and voice traffic.
Two new digital PLLs claim industry-leading jitter performance and superior features to ensure the reliable transport of data, multimedia and voice traffic Combining enhanced features such as flexible reference monitoring and superior holdover capabilities with jitter performance of less than 0.5ns - several times better than competing devices - the ZL30100/1 digital PLLs easily and cost-effectively meet Stratum 3 and Stratum 4/4E requirements for access, edge, and customer premises equipment
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
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"Zarlink is the innovator in designing a wide range of off-the-shelf, silicon-based digital timing devices", said Darren Ladouceur, Marketing Manager, Timing and Synchronization, Zarlink Semiconductor.
"Compared with competing devices, this new series of digital PLLs delivers superior performance and enhanced features for externally timed and line-timed systems".
The ZL30101 digital PLL is well suited for central office and edge equipment requiring Stratum 3 timing, such as master DSLAMs (digital subscriber line access multiplexers) powering consumer broadband access.
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Central office equipment extracts its timing information from dedicated synchronisation references.
The holdover capability of the premier ZL30101 timing chip allows externally timed network equipment to receive and send data even when the network synchronisation source is temporarily lost or interrupted.
This ensures there is no service disruption for subscribers.
In comparison, line-timed customer premises and access equipment, including VoIP Gateways that support enterprise communications services, extracts its timing information from the same T1/E1 trunk lines that carry data.
Line-timed equipment requires highly reliable clocks synchronised with central office equipment to ensure the proper flow of data, multimedia and voice traffic between emerging and legacy networks.
The ZL30100 digital PLL allows designers to cost-effectively design a timing solution meeting Stratum 4/4E requirements for a range of line-timed equipment - from PBXs and remote access DSLAMs, to wireless basestations, enterprise routers and gateways.
The device provides clocks meeting international standards during normal operation, and enhanced reference monitoring and reference switching capabilities that allow the PLL to switch the source of timing from a failed interface to an operational interface without losing data.
Major equipment vendors are now evaluating Zarlink's ZL30100/1 digital PLLs for use in wireless basestations, DSLAMs, PBXs, VoIP gateways and routers.
Offering superior performance and enhanced capabilities, the ZL30100/1 digital PLLs produce extremely stable and reliable clocks with holdover and reference switching features.
The devices are pin-to-pin compatible, allowing designers to easily migrate from a Stratum 4 to a Stratum 3 clock as required.
On their inputs, both timing chips accept two references and automatically synchronise to any combination of clocks operating at 8kHz, 1.544MHz, 2.048MHz, 8.192MHz or 16.384MHz.
For equipment with access to multiple timing references, the chips ensure system reliability by monitoring references for accuracy.
If a problem is detected, the devices' reference switching capability enables systems to switch between timing references to avoid a potential loss of services.
Paired with a 20MHz oscillator, the ZL30101 timing chip provides precise reference monitoring meeting Stratum 3 specifications.
The ZL30100 device, with selectable reference monitoring, allows designers to choose from a range of cost-effective clock oscillators or crystals that meets their equipment requirements.
The ZL30100/1 digital PLLs deliver the industry's most complete range of output clocks for Stratum 3 and Stratum 4/4E systems, including T1/E1 interface clocks and 4.096, 8.192, 16.384, 32.768 and 65.536MHz clocks and associated frame pulses, with industry-leading jitter performance of less than 0.5ns peak-to-peak.
If the source of network synchronisation is temporarily lost, the ZL30100/1 digital PLLs switch automatically into holdover mode, and continue to generate output clocks based on data collected from past reference signals.
The ZL30100/1 digital PLLs deliver exceptional holdover performance of 0.01ppm for Stratum 3 systems, and 0.15ppm for Stratum 4/4E systems.
Zarlink's digital PLLs comply with Telcordia's GR-1244-Core for Stratum 3 and Stratum 4/4E, ITU-T's G.823 and G.824, and ANSI T1.403.
The ZL30100/1 digital PLLs are in volume production.
The chips are offered in a 64-pin TQFP (thin quad flatpack) measuring 10 x 10mm.
In 1000-off quantities, the ZL30100 device is priced at US $10 and the ZL30101 chip at US $20.
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