Packet processors meet latest TDM specs

The ZL50111 family of TDM-over-IP packet processors are the first devices to meet the protocols outlined in the industry's newest recommendation for TDM circuit transmission over packet networks.

Zarlink reckons its ZL50111 family of TDM-over-IP packet processors are the industry's first commercially available devices to fully meet the protocols outlined in the industry's newest recommendation for TDM (time division multiplexing) circuit transmission over packet networks.

The ITU-T recently released Recommendation Y.1413 - TDM-MPLS network interworking - User plane interworking.

The recommendation outlines the TDM timing, signalling, service quality and alarm integrity required when legacy voice, data and multimedia traffic is carried over an MPLS (multiprotocol label switching) network up to DS3 or E3 rates.

Zarlink's ZL50111 family of TDM-over-IP packet processors complies fully with both the structure aware and structure agnostic modes of operation outlined by Recommendation Y.1413.

Currently in full production, the three-chip ZL50111 family uses CESoP (circuit emulation services over packet) technology to "tunnel" many forms of Layer 2 TDM traffic over any packet network.

Zarlink's TDM-over-IP processors are simple to implement, support a wide range of services, and deliver carrier-grade quality.

Service providers are stepping up investments in PSN equipment in an effort to lower operating their costs by consolidating networks and to meet the growing demand for IP-based services, such as voice-over-packet.

For example, MPLS-enabled switches are being deployed to efficiently carry all types of network traffic over a converged PSN infrastructure.

However, service providers must still cost-effectively transport profitable TDM-based services, with guaranteed quality, over new PSNs.

The ZL50111 processor family fully addresses the critical timing and service quality concerns associated with TDM-over-IP technology, as outlined in the ITU-T Recommendation.

To deliver carrier-grade quality, techniques are employed both within the hardware and software to ensure submillisecond latencies through the devices, coupled with highly accurate clock recovery and synchronisation.

Quality is enhanced by advanced on-chip queuing mechanisms that minimise the effects of network latency by giving time-sensitive TDM packets priority over data packets in processing queues.

"Service providers are demanding networking equipment that allows them to plan an effective migration to an all-IP network while still supporting revenue-generating legacy services", said Jeremy Lewis, Product Line Marketing Manager, Packet Processing, Zarlink Semiconductor.

"The ZL50111 TDM-over-IP processors were designed with features and performance in anticipation of the industry's stringent interworking requirements".

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