Product category:
Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: ZL30102 and ZL30105
Edited by the Electronicstalk Editorial
Team on 10 June 2004
Digital PLLs claim carrier-class
performance
Two new digital PLLs for timing cards enable carrier-class reliability and performance in proprietary and standardised networking system architectures, including H.110 and Advanced TCA.
Two new digital PLLs for timing cards enable carrier-class reliability and performance in proprietary and standardised networking system architectures, including H.110 and Advanced TCA The ZL30102 and ZL30105 products target exciting high-growth networking equipment markets, including digital subscriber line access multiplexers, wireless base stations, VoIP routers and gateways, as well as add/drop multiplexers, crossconnects and PBXs
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
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"Our new DPLLs help customers deliver carrier-class services-availability, performance, and system maintainability in a wide range of SDH, PDH and datacomms applications", said Andy Turudic, Product Line Marketing Manager, Network Communications, Zarlink Semiconductor.
"Using proprietary spectrum-shaping and clock-generation algorithms, these DPLLs are well positioned for new design-ins and to take market share with competitive pricing, industry-leading jitter performance, and value-added features such as redundant, Stratum 3/4/4E compliant clocks, and frame-pulses".
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The ZL30102 and ZL30105 chips also generate ST-Bus, supporting Zarlink's full line of TDM switching solutions, and other TDM clock and framing signals that are phase aligned to one of three network references or to another system primary-clock reference.
The chips accept three input references and synchronise to 2 or 8 kHz, or 1.544, 2.048, 8.192, 16.384 or 19.44MHz inputs.
They deliver significant improvements in lock time, support manual or automatic reference switching, and have excellent holdover accuracy - all key elements in timing performance.
Both devices are managed through a simple hardware control interface.
With networks trending toward higher speed, IP-based equipment, implementing advanced timing and synchronisation is more challenging.
Designers striving to improve system reliability are demanding redundant timing control and monitoring to ensure continued operation during network upgrades or disruptions.
Zarlink's new DPLLs provide constant monitoring of the clocks and maintain close phase alignment between a "primary" and "secondary" clock under network, or intrasystem, jitter and wander conditions - allowing hitless, manual or automatic switching to a working secondary clock if the primary clock begins to exhibit failure.
The ZL30102 device builds on the ZL30100 DPLL, released earlier this year, and is the most comprehensive T1/E1 terminal equipment DPLL on the market.
The ZL30102 timing chip meets Stratum 4/4E clock requirements and is applicable to H.110 and similar proprietary systems.
The chip's outputs also generate the industry's lowest jitter - below 0.6ns peak-peak, with jitter filtering from 1.8Hz.
The ZL30105 chip is a simple-to-use Stratum 3/4/4E SDH DPLL and includes ITU-T G.813 option 1 compliance, reference clock monitoring, and automatic or manual hitless reference clock selection features.
Using proprietary clock-generation techniques, the device simultaneously generates four harmonically unrelated families of reference-locked SDH and PDH clocks - 1.544, 2.048 and 19.44MHz and DS2/E2/DS3/E3 - for flexible timing card applications.
In competing PLLs, a harmonic relationship is generally needed to produce locked clock outputs, precluding them from producing numerous clocks.
The ZL30105 chip also directly provides low-jitter clock and frame-pulse support for the emerging Advanced TCA bus.
This bus is expected to proliferate across telecomms and datacomms equipment, analogous to the use of PCI cards as building blocks in today's computer and test systems.
The proprietary jitter shaping, cleanup, and filtering techniques in the ZL30105 DPLL - resulting in 600ps of worst-case unfiltered peak-to-peak jitter and exceeding stringent OC-3 jitter requirements - enables its use in tandem with a Zarlink frequency multiplying analogue PLL to produce even higher line rate clocks, with low combined jitter, than those supported by the device's 19.44MHz output.
Zarlink's DPLLs meet the requirements of Telcordia GR-1244-CORE for Stratum 3/4/4E, ITU-T G.823, G.824, and G.813 option 1, and ANSI T1.403.
The ZL30102 and ZL30105 DPLLs are in volume production.
The chips are offered in a 64-pin TQFP (thin quad flat pack) measuring 10 x 10mm.
In 1000-off quantities, the ZL30102 device is priced at US $22.50 and the ZL30105 chip at US $27.50.
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