Digital and analogue PLLs combine for Sonet

A new pair of timing chips combine to deliver the industry's most complete feature set and best performance for Sonet/SDH and PDH systems.

A new pair of timing chips combine to deliver the industry's most complete feature set and best performance for Sonet/SDH and PDH systems.

Zarlink's new digital and analogue PLLs are targeted at line cards used in a broad range of equipment from the enterprise to the network core.

With the deployment of increasingly complex network architectures and higher-speed transmission systems, achieving reliable network timing and synchronisation is becoming more challenging.

To ensure carrier-grade performance, equipment designers must use combinations of digital and analogue PLLs that work in tandem to deliver superior timing functionality and performance, while meeting system compliance requirements with substantial jitter margins.

However, current market offerings require the integration of multiple products from disparate vendors, often resulting in less-than-optimum jitter performance and feature sets.

Zarlink's two new chips directly address these fundamental issues.

The ZL30106 digital PLL beats competing products with an unparalleled OC-3 jitter compliance margin and offers the industry's fullest feature set, including hitless reference switching, reference monitoring and holdover.

When used in combination with the ZL30416 analogue PLL, Zarlink's proprietary digital PLL frequency synthesis technique minimises low frequency phase noise, allowing designers to optimise the analogue PLL bandwidth and achieve overall superior jitter performance and error-free transmission.

"Zarlink is delivering a complete range of digital and analogue timing products for high-growth broadband networking systems such as gateways, DSLAMs, metro add-drop multiplexers, routers and high-speed last mile equipment", said Darren Ladouceur, Marketing Manager, Timing and Synchronisation, Zarlink Semiconductor.

"Together with our PLLs for timing cards, our complete line card offering demonstrates the market's highest standards of timing functionality and jitter management".

"We are providing customers with a single-vendor, characterised timing solution for carrier-class timing systems, resulting in reduced time-to-market and cost".

Jitter shaping is the management and filtration of clock outputs in a timing system.

Typical digital PLLs produce wideband phase noise across all frequencies, making the analogue PLL filtering more challenging, and degrading overall jitter performance.

Zarlink's frequency digital PLL synthesis technique effectively filters low-frequency phase noise, permitting designers to focus the analogue PLL on its core attribute - eliminating high-frequency phase noise.

Zarlink has demonstrated that this combination of devices exhibits optimum low-frequency behaviour and superior overall jitter performance.

The ZL30106 digital PLL synchronises Sonet/SDH and PDH line cards.

In addition to industry-leading jitter performance of 20ps RMS, the chip is distinguished from competing digital PLLs in its ability to synchronise primary and secondary input references to clock-and-sync pulse pairs.

The device accepts three input references, provides a range of output clocks, and achieves holdover frequency accuracy of 0.01ppm.

The ZL30106 digital PLL provides the choice of manual or automatic hitless reference switching.

The ZL30416 analogue PLL performs jitter attenuation and rate conversion for Sonet/SDH equipment, and is specifically designed to meet the feature and performance requirements of line card applications from OC-3/STM-1 up to OC-192/STM-64 transmission rates.

The chip generates ultra-low-jitter output clocks that meet Telcordia GR-253-Core jitter specifications up to and including OC-192 and is compliant with G.813 Option 1 and Option 2 jitter generation requirements up to and including STM-64.

The ZL30106 and ZL30416 chips are in volume production.

The ZL30106 digital PLL is offered in a 64-pin TQFP and in 1000-off quantities is priced at US $15.00.

The ZL30416 analogue PLL is offered in a 64-ball chip BGA and is priced at US $36.19 in 1000-off quantities.

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