Product category:
Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: ZL50111 family
Edited by the Electronicstalk Editorial
Team on 06 October 2004
Processors package up to four circuits
Following the launch of three low-density CES-over-packet processors, Zarlink Semiconductor now offers the industry's only end-to-end portfolio of circuit-to-packet devices.
Following the launch of three low-density CES (circuit emulation services)-over-packet processors, Zarlink Semiconductor now offers the industry's only end-to-end portfolio of circuit-to-packet devices The three-chip ZL50120 family uses CES-over-packet technology to seamlessly "tunnel" one, two or four streams of TDM voice, video and data traffic, with associated timing and signalling, across Ethernet, IP and MPLS (multiprotocol label switching) networks
This article was originally published on Electronicstalk on 23 Sep 2003 at 8.00am (UK)
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Packet processors meet latest TDM specs
The ZL50111 family of TDM-over-IP packet processors are the first devices to meet the protocols outlined in the industry's newest recommendation for TDM circuit transmission over packet networks.
Complementing the ZL50111 family of high-density CES-over-packet processors, Zarlink delivers circuit-to-packet bridging devices that handle up to 32 streams of TDM traffic.
"Dealing with the transport of legacy services is an important element in the rollout of Enterprise packet networks", said Jeremy Lewis, Product Line Manager, Packet Processing, Zarlink Semiconductor.
"With our new low-density packet processors, carriers can build out cost-effective packet networks to the enterprise, without service disruptions to, or requiring significant infrastructure upgrades from, their customers".
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Packet processors unite US and Korean designs
Four equipment manufacturers in the USA and Korea are developing a range of networking equipment based on the ZL50111 family of TDM-over-IP packet processors.
Packet processor for broadband networks
Mitel Semiconductor has introduced the world's highest density AAL2 segmentation and re-assembly (SAR) device.
Quality of service is key to Gigabit Ethernet ICs
The MVTX2800 family of Gigabit Ethernet switching ICs from Zarlink Semiconductor deliver full-wire speed forwarding and leading quality of service features to metropolitan optical access equipment.
Facing growing data traffic volumes and increased competition from cable providers, carriers are under pressure to quickly extend their packet networks.
At the same time, enterprise customers are demanding high-bandwidth Ethernet connections without sacrificing service quality or requiring a "rip and replace" equipment upgrade.
With Zarlink's CES-over-packet technology, carriers can expand the reach of their packet networks and offer valuable new services to retain and attract customers.
By using a CES-over-packet-enabled remote concentrator located at the customer site or a roadside pedestal, TDM traffic can be emulated across a converged packet network that cost-effectively delivers multiple services to the end user.
Similarly, mobile service operators who previously relied on expensive T1/E1 leased lines to backhaul traffic from the cell site, can instead emulate TDM traffic over a cost-effective fibre or microwave Ethernet link.
This protects service operators with significant investments in TDM and ATM-based networks.
Zarlink's CES-over-packet devices also fit seamlessly into FTTx (fibre-to-the-x) systems, including ePONs (Ethernet passive optical networks) that meet the recently ratified IEEE802.3ah standard.
In addition, Zarlink's CES-over-packet technology allows end customers to protect their investment in legacy networking equipment, while enjoying the operating cost savings afforded by a converged packet network.
Zarlink recently announced that four equipment manufacturers in the USA and Korea - Comtec Systems, Eagle Telephonics, Intronics and Rivertree Networks - are responding to user demand by designing Zarlink CES-over-packet processors into new media gateways, central office and Ethernet switching products that transport TDM services over packet networks.
This year Zarlink also announced interoperability between the ZL50111 processor and the Arranto 100TE multiservice TDM-over-packet gateway from Redux Communications; and with the AXN multiservice packet concentrator with CESoP support, from Axerra Networks.
The new ZL50120 packet processor family consists of three devices.
The ZL50118 chip supports a single T1/E1 stream, the ZL50119 device supports two T1/E1 streams, and the ZL50120 chip supports four T1/E1 streams.
All three processors include a user-side Fast Ethernet port, allowing them to aggregate both Ethernet and TDM traffic and significantly simplify system-level design.
Achieving precise network timing is a key challenge when delivering constant-bitrate voice traffic over variable-bitrate PSNs.
Zarlink's low-density ZL50120 processor family implements more than 15 patent-pending hardware/software processing techniques for clock recovery and synchronisation to ensure carrier-class voice quality.
Voice quality is also enhanced by advanced on-chip quality of service mechanisms, such as weighted fair queuing and strict priority, which minimise the effects of network latency by giving time-sensitive voice packets priority over data packets in processing queues.
The devices deliver an extremely low and stable latency connection, with intrinsic delays of less than 250us.
The ZL50120 family simplifies board-level design for manufacturers.
With on-chip SRAM capable of handling network delays of more than 100ms with comparable packet delay variations, line card designers do not require external memory devices.
The processors also provide direct connectivity to a LIU (line interface unit) or framer on the TDM side, and to an Ethernet physical layer device on the packet side, providing a very minimal chip-count solution.
Zarlink's ZL50120 processor family complies with all circuit emulation services draft standards currently under development with the Metro Ethernet Forum, Internet Engineering Task Force and the MPLS-Frame Relay Alliance, as well as the recently published ITU-T Y.143 recommendation.
The ZL50120 packet processors are in volume production.
A complete reference design, an evaluation board and a software API support the chips.
All three devices are offered in 23 x 23mm, 324-ball plastic BGA packages.
In quantities of 5000, the ZL50118 is priced at US $39.15, the ZL50119 at US $49.59, and the ZL50120 at US $66.12.
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