Digital timing chips for networking equipment

Zarlink Semiconductor has expanded its portfolio with the ZL30109 device, a new DPLL that delivers added flexibility and carrier-class performance for broadband equipment.

Zarlink Semiconductor, a leader in timing devices for T1/E1 or PDH (plesiochronous digital hierarchy) networking, has expanded its portfolio with the ZL30109 device, a new DPLL that delivers added flexibility and carrier-class performance for broadband equipment.

Zarlink offers the most comprehensive line of PDH timing chips for worldwide network applications ranging from line card clock generation and multiplication to timing control in central office equipment.

The ZL30109 chip is a monolithic silicon device ideal for design into high-speed customer premises and access networking equipment, including DSLAMs (digital subscriber line access multiplexers), VoIP gateways, and IP-PBXs.

Functioning as a central timing device, the chip accepts a wide range of reference frequencies including an additional 2 kHz frame pulse and a 19.44 MHz clock, making it compatible with a wider range of applications.

Footprint-compatible with Zarlink's entire family of T1/E1 DPLLs, the ZL30109 chip complements Zarlink's portfolio of analog clock-multiplier PLLs.

The device combines features such as flexible reference monitoring and superior holdover capability with jitter performance of better than 0.5 ns (nanoseconds), easily meeting Stratum 4/4E requirements while providing the 19.44MHz SONET/SDH frequency.

"The ZL30109 DPLL offers a cost-effective, high-performance solution for Stratum 4 and 4E designs," said Andy Turudic, product line marketing manager, Network Communications, Zarlink Semiconductor.

"Our customers can also use the same board layout and components to implement more stringent Stratum 3 applications - increasing their design flexibility and time-to-market." Fully featured PDH DPLL The ZL30109 device is pin-to-pin compatible with the ZL30100 and ZL30101 DPLLs, released earlier this year.

The new chip produces extremely stable and reliable clocks, allowing designers to quickly migrate from a Stratum 4/4E to a Stratum 3 clock with the same circuit board design.

All features and modes are hardware-selected, minimizing the need for complex software drivers or an external microprocessor.

The ZL30109 timing chip accepts two reference clock inputs and automatically synchronizes to any clock operating at a frequency of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz.

The device cleans up the jitter from these input clocks using Zarlink's unique jitter shaping techniques and outputs the following frequencies: 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz, 32.768 MHz and 65.536 MHz and 19.44 MHz.

Carrier-class reliability As the primary timing control in customer premise and access equipment, the ZL30109 chip must ensure continued operation during network disruptions or upgrades.

Zarlink's DPLL continuously monitors the input reference clocks and provides hitless reference switching upon detection of a bad or failed reference clock.

The DPLL maintains stable and reliable output clocks in the presence of network or intra-system jitter and wander conditions.

If the source of network synchronization is temporarily lost, the ZL30109 device automatically switches into holdover mode and continues to generate output clocks based on data collected from past reference signals.

Exceptional holdover performance of 0.15 ppm (parts per million) for Stratum 4/4E systems is delivered.

Zarlink's DPLL meets the requirements of Telcordia GR-1244-CORE for Stratum 3/4/4E, ITU-T G.823, G.824, and G.813 option 1, and ANSI (American National Standards Institute) T1.403.

Availability, packaging and price The ZL30109 DPLL is now in volume production, offered in a 64-pin TQFP (thin quad flat pack) measuring 10x10 mm.

In 1K quantities, the ZL30109 chip is priced at US$13.50 each.

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