Packet processors meet latest recommendations

Zarlink's CES-over-packet processors comply with the industry's newest recommendations for TDM circuit transmission over MPLS and metro Ethernet networks.

Zarlink's entire line of Circuit Emulation Services (CES)-over-packet processors fully complies with the industry's newest recommendations for TDM circuit transmission over MPLS (multiprotocol label switching) and metro Ethernet networks.

The MPLS and Frame Relay Alliance (MFA) recently released implementation agreement MFA 8.0.0, which addresses the encapsulation formats and setup and teardown of connections for carrying TDM circuits across MPLS networks.

The MFA's new agreement simplifies TDM transport over MPLS, allowing network operators to move towards a single, converged network delivering voice, video and data services.

The Metro Ethernet Forum (MEF) also ratified new technical specifications for carrier-class Ethernet.

Specification MEF 8 defines the implementation for emulating PDH (plesiochronous digital hierarchy) circuits over metro Ethernet networks, and outlines requirements for employing CES over Metro Ethernet networks as defined in the earlier MEF 3 technical specification.

MEF 8, along with new specifications addressing test procedures and network management for Ethernet services, will guide the rollout of metro Ethernet as a carrier-class service delivery technology.

Zarlink's three-device ZL50111 high-density and three-device ZL50120 low-density families of CES-over-packet processors seamlessly "tunnel" from one to 32 streams of TDM voice, video and data traffic, with associated timing and signalling, across MPLS, Ethernet and IP networks.

All six devices are in full production.

The ZL50111 and ZL50120 families fully address the performance specifications outlined by the MFA and MEF.

To achieve precise network timing when delivering constant bitrate voice traffic over variable-bitrate packet networks, Zarlink's CES-over-packet devices employ hardware and software processing techniques for highly accurate clock recovery and synchronisation.

Voice quality is enhanced by advanced on-chip QoS (quality of service) mechanisms, such as weighted fair queuing and strict priority, that minimise the effects of network latency by giving time-sensitive TDM packets priority over data packets in processing queues.

"Zarlink's CES-over-packet processors were designed with features and performance in anticipation of the industry's performance specifications", said Jeremy Lewis, Product Line Marketing Manager, Packet Processing, Zarlink Semiconductor.

"With Zarlink's packet processor technology, carriers can cost-effectively build-out packet networks to the enterprise, while supporting legacy services and without sacrificing quality or requiring significant infrastructure upgrades".

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