Product category:
Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: ZL50117 family
Edited by the Electronicstalk Editorial
Team on 21 December 2004
Processors tunnel TDM streams over IP
and wireless
Three new low-density CES-over-packet processors will allow network operators to cost-effectively support TDM voice, video and data services over expanding metro Ethernet and wireless networks.
Zarlink Semiconductor has launched three low-density circuit-emulation-services-over-packet processors that allow network operators to cost-effectively support TDM voice, video and data services over expanding metro Ethernet and wireless networks The three-chip ZL50117 family uses CES-over-packet technology to seamlessly "tunnel" one, two or four streams of TDM traffic, with associated timing and signalling, across Ethernet, IP and MPLS (multiprotocol label switching) networks
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
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Complementing Zarlink's ZL50120 family of fully featured low-density packet processors, these new devices allow service providers to easily deliver TDM legacy services to their customer.
"By adding Zarlink's CES-over-packet expertise within a metro Ethernet network, service providers can cost-effectively carry highly profitable TDM traffic alongside packet-based services", said Jeremy Lewis, Product Line Manager, Timing and Convergence, Zarlink Semiconductor.
"Similarly, as wireless operators evolve towards an IP infrastructure, CES-over-packet technology allows them to reduce operating costs and maintain services without requiring a significant infrastructure upgrade".
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Faced with growing data traffic volumes and increased competition, service providers are aggressively extending flexible metro Ethernet networks closer to the customer.
Despite the operating benefits afforded by Ethernet networks, services providers cannot ignore the revenues generated by legacy services from home and enterprise customers.
With Zarlink's new low-density CES-over-packet devices, network operators rolling out an Ethernet-based network can easily support TDM services.
CES-over-packet allows end customers to maintain their investment in legacy networking equipment and enjoy the lower costs of a packet network, without requiring a "rip and replace" infrastructure overhaul.
Traditionally, wireless network operators have relied on expensive T1/E1 lines to backhaul traffic from basestations to basestations controllers.
To reduce operating expenses and meet standards from the 3GPP and other organisations, they are now replacing T1/E1 access links with less expensive Gigabit Ethernet-based packet connections.
Zarlink's CES-over-packet technology can be easily designed into line cards in the basestation and basestation controller to seamlessly carry TDM traffic across the Ethernet connection.
TDM traffic timing information is carried end-to-end across the packet network to ensure service still meets relevant T1/E1 standards.
Similarly, with Wi-Fi and WiMAX technologies gaining acceptance, CES-over-packet allows the wireless backhaul of T1/E1 trunks across an Ethernet-based local area network at a lower cost than a microwave link.
Zarlink has well-established experience delivering TDM-based services to customers, at the system and silicon levels.
With these new CES-over-packet devices, Zarlink has extended this expertise into the packet network.
The processors deliver critical synchronisation performance that surpasses G.823/G.824 and T1.403 Traffic Interface requirements over a wide variety of packet networks.
The ZL50117 packet processor family consists of three devices.
The ZL50115 chip supports a single T1/E1 stream, the ZL50116 device supports two T1/E1 streams, whereas the ZL50117 chip supports four T1/E1 streams.
Zarlink's complete CES-over-packet processor family includes a comprehensive range of lightly- and fully-featured devices capable of handling from one to 32 streams of TDM traffic.
Zarlink's ZL50117 family simplifies board-level design.
With on-chip SRAM circuitry capable of handling network delays of more than 100ms and comparable packet delay variations, external memory devices are not required.
This capability far exceeds customer performance requirements, which range from tens of milliseconds for network delay up to 10 to 15s of packet delay variation.
Zarlink's ZL50117 family complies with the ITU's recommendation ITU Y.1413 on TDM-over-MPLS networks, and implementation agreements for circuit emulation services over MPLS and metro Ethernet networks, from the MPLS-Frame Relay Alliance and the Metro Ethernet Forum.
The processor family also complies with TDM-over-packet standards under development by the Internet Engineering Task Force.
The ZL50117 packet processors are in volume production.
A complete reference design, an evaluation board and a software API support the chips.
All three devices are offered in 23 x 23mm, 324-ball PBGA (plastic ball grid array) packages.
In quantities of 5000, the ZL50115 is priced at US $32.19, the ZL50116 at US $42.63, and the ZL50117 at US $59.16.
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