Product category:
Communications ICs (Wired)
News Release from: Zarlink Semiconductor | Subject: ZL30117
Edited by the Electronicstalk Editorial
Team on 14 February 2006
Synchroniser solves timing challenges
A single-chip ultra-low-jitter synchroniser solves the timing challenges posed by the popular AdvancedTCA, AMC and MicroTCA architectures.
Zarlink Semiconductor has launched a single-chip, ultra-low-jitter synchroniser that solves the timing challenges posed by the popular AdvancedTCA (telecommunications computing architecture), AMC (advanced mezzanine card) and MicroTCA architectures Feature rich and highly integrated, the ZL30117 chip meets or exceeds international standards and is the smallest and lowest power synchroniser for open-platform telecom architectures
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
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By using standard hardware and software components from multiple vendors, ATCA, AMC, and MicroTCA reduce the time and cost-to-market of high-performance, high-density systems, but present challenges for achieving carrier-grade synchronisation reliability.
ATCA, AMC and MicroTCA are ideal for telecom applications, including 3G wireless mobile infrastructures and wireline equipment such as media gateways and MSPPs (multi-service provisioning platforms).
Research indicates that the market for the commercial building blocks of ATCA equipment alone will grow from almost zero in the early 2000s to US $3.7 billion by 2007.
The ZL30117 synchroniser offers robust features for AMCs used in ATCA and MicroTCA designs.
While easy to use and adaptable, AMCs do not provide redundant timing reference inputs to support carrier-grade timing.
The holdover capability of the ZL30117 chip enables it to ride out the complete loss of its incoming reference, which can occur when switching from a failed clock unit to a backup clock unit.
The ZL30117 PLL continues to operate in full compliance with network requirements for several seconds after losing its reference, allowing time for the system to provide another reference source to the AMC.
The ZL30117 device accepts three reference inputs, supporting clock frequencies in any multiple of 8kHz up to 77.76MHz, as well as supporting 2kHz.
The ZL30117 chip can directly lock to any of the standard clock input frequencies available to an AMC in an ATCA or MicroTCA application.
The ZL30117 device is the newest in Zarlink's family of synchronisation chips.
The ZL30116 and ZL30119 devices, introduced in December 2005, are the industry's smallest programmable digital/analogue PLLs for system and line card synchronisation in Sonet/SDH MSPPs and multiservice edge products.
Only Zarlink's devices combine the capabilities to lock to 8kHz references, smoothly switch between references and generate ultra-low-jitter clocks.
Most digital PLLs generate too much jitter for interfaces at rates above OC-3, necessitating a separate analogue PLL to "clean up" the noise.
Multi-chip combinations or modules may be as large as one square inch.
Zarlink is first to deliver a single-chip synchroniser capable of generating less than 1ps RMS of jitter in full compliance with OC-48 and STM-16 requirements.
The ZL30117 PLL consumes less than 0.9W of power and measures just 9 x 9mm.
The ZL30117 PLL is available now.
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