Timing and synchronisation for Ethernet line cards

Single-chip Gigabit Ethernet line card synchroniser allows service providers to seamlessly and economically deliver time-critical applications over packet-based networks.

Zarlink Semiconductor has expanded its family of synchronous Ethernet timing solutions, with a new single-chip Gigabit Ethernet line card synchroniser that allows service providers to seamlessly and economically deliver time-critical applications over packet-based networks.

Available now, the ZL30107 chip provides timing and synchronisation for Ethernet line cards in next-generation networking equipment supporting circuit services over IP-based architectures.

Integrating independent analogue and digital PLLs, the device synchronises with standard telecom and Ethernet clocks and generates an IEEE802.3 jitter compliant 25MHz Gigabit Ethernet output clock.

Backed by Zarlink's leading timing and synchronisation expertise, no competing device can match the performance and level of integration at the price point supported by the ZL30107 device.

"Synchronous Ethernet is a key technology as service providers aggressively seek new ways to more efficiently support time-sensitive applications over packet networks", said Darren Ladouceur, Marketing Manager, Timing and Synchronisation, Zarlink Semiconductor.

"Building on our established synchronous Ethernet timing solutions, the ZL30107 chip allows manufacturers to easily build timing capabilities into next-generation networking equipment".

Currently, service providers must operate a number of different networks and deploy costly external mechanisms to support legacy services over IP architectures.

For example, network synchronisation between remote MSAPs (multiservice access platforms) are connected to central office equipment via T1/E1 or Sonet/SDH links.

In comparison, synchronous Ethernet technology allows service providers to deliver all services over a single converged, high-bandwidth, synchronous Ethernet link.

The ZL30107 device supports synchronous, holdover and asynchronous free-run modes of operation.

In synchronous operation, the ZL30107 PLL replaces the free-running reference clock usually provided by an oscillator with a network timing reference.

The device accepts three references and performs hitless reference switching.

The integrated DPLL automatically synchronises to one of a predefined set of standard telecom frequencies ranging from 2kHz to 77.76MHz in addition to 25MHz.

The chip generates a very low jitter 25MHz Gigabit Ethernet output clock.

When all references fail the device automatically enters holdover mode and continues to generate an output clock based on frequency data collected from past reference signals.

The chip defaults to asynchronous free-run mode, where the DPLL generates an output clock with frequency accuracy equal to an external oscillator or low-cost crystal.

This allows equipment manufacturers to "build-in" synchronous Ethernet capabilities in next-generation networking equipment.

Services providers can then easily enable synchronous Ethernet capability when it is required.

The ZL30107 chip is in volume production and offered in a 9 x 9mm, 64-pin CABGA package.

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