Power management technology updated

Zarlink Semiconductor's new WPX power management process allows designs to be developed using fewer layers, reducing manufacturing costs.

Zarlink Semiconductor has released a new modular low-cost version of its WPX power management process technology.

The modular WPX power management process affords greater flexibility.

Designs can now be developed using fewer layers in the process to greatly reduce manufacturing costs.

The WPX process has been specifically developed for consumer and professional applications, including dc-dc power bricks, mobile telephone battery power management, linear and switching regulators, and all other linear power management applications.

The WPX power management process technology is a versatile, low-capacitance linear bipolar process providing excellent functionality at a low cost.

The lateral PNP transistors have been improved along with better control of the gain functions.

Features such as high-value poly resistors and nitride capacitors and two-layer metal allow low-current circuits to be built with high packing densities.

The resulting designs have very low leakage currents and low flicker noise - important functions in critical power management designs.

"Our customers demand cost-effective manufacturing processes that support a technological advantage over their competitors", said Dr Peter Osborne, Chief Technology Officer, Zarlink Analog Foundry.

"This modular process provides that advantage".

"We can deliver more die per wafer, at higher yields with outstanding technology and now at a competitively priced cost per wafer".

"In improving this process, we have considered both the needs of our own customers as well as the demands of their end-customers".

The Zarlink Analog Foundry uses 150mm technology to provide end-to-end foundry service, from design expertise and engineering support to leading processes and technologies.

The silicon solutions provide customers a system and sub-system cost advantage with processes that support designs with the smallest die, highest yielding wafers, highest functional integration and highest operating frequency at high voltage.

The Foundry's Design Services group is a broad-based team with significant experience and expertise in silicon IC design.

These include a comprehensive autographics service, front-to-back end design capability on third-party CAD software tools, and ESD (electrostatic discharge) consultation.

A complete plug and play design environment is offered, comprising schematic capture, layout and comprehensive DRC and LVS (layout versus schematic) design verification.

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