Product category:
Frequency Control Components
News Release from: Zarlink Semiconductor | Subject: Synchronous Ethernet timing products
Edited by the Electronicstalk Editorial
Team on 20 July 2007
Time is right for Synchronous Ethernet
Integrated analogue/digital PLLs meet all Synchronous Ethernet timing requirements, including the latest recommendation from the ITU-T.
Zarlink Semiconductor has begun sampling a range of integrated analogue/digital PLLs that meet all Synchronous Ethernet timing requirements, including the latest recommendation from the ITU-T Consented in June 2007, the ITU-T G.8262 recommendation (former G.paclock) outlines the minimum performance requirements for timing devices used to synchronise networking equipment that uses Synchronous Ethernet
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
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The recommendation defines PLL performance characteristics, including wander, jitter, phase transients, clock bandwidth, frequency accuracy and holdover.
Synchronous Ethernet technology is being deployed in DSLAMs (digital subscriber line access multiplexers), routers, MSSPs (multiservice switching platforms), PON (passive optical network) and multiservice access equipment to enable voice, data, video and legacy services over a converged, high-bandwidth, Synchronous Ethernet link.
Previously, service providers had to maintain dedicated T1/E1 or Sonet/SDH links to support time-critical services over packet networks.
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Building on the previously released ZL30107 and ZL30120 Gigabit Ethernet line card synchronisers, Zarlink is now sampling its second generation of multirate, 1 and 10Gbit/s Ethernet analogue/digital PLL products supporting all Ethernet frequencies with the option to support independent transmit and receive timing paths.
Zarlink's new Synchronous Ethernet products support both 1 and 10Gbit/s Ethernet frequencies or Sonet/SDH frequencies.
The devices also feature both single-ended and differential outputs.
Integrated dual PLLs in one package support transmit and receive timing paths, allowing the devices to seamlessly convert backplane and PHY clocks.
In the transmit path the products support rate conversion from standard telecom or Ethernet frequencies and provide jitter attenuation to generate a low-jitter Ethernet clock for the PHY.
In the receive path the products rate convert the Synchronous Ethernet recovered clocks to the backplane frequency, which then feeds back to the system timing card.
In comparison, competing approaches would require multiple devices to implement transmit and receive timing paths.
Zarlink's Synchronous Ethernet products support multiple input references, hitless reference switching, holdover, low-jitter Ethernet outputs and programmable clock and frame pulse outputs.
Zarlink's timing card products also provide wander filtering meeting G.8262 requirements.
The products combine leading performance and features to ease system integration, improve power dissipation and lower component count and reduce footprint requirements.
Zarlink's expanded family of Synchronous Ethernet timing products is now sampling.
Zarlink is also sampling new devices that combine Synchronous Ethernet and IEEE1588 functionality for applications that require accurate timing frequencies and time-of-day capabilities.
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