Product category:
Intellectual Property Cores
News Release from: MIPS Technologies | Subject: MIPS64 5Kf
Edited by the Electronicstalk Editorial
Team on 14 June 2001
64bit soft core has integral
floating-point unit
In response to customer demand for a 64bit synthesisable processor core with floating point, MIPS Technologies has introduced the MIPS64 5Kf core.
In response to customer demand for a 64bit synthesisable processor core with floating point to improve performance throughput in next-generation consumer products, MIPS Technologies has introduced the MIPS64 5Kf core LSI Logic, Atmel and Texas Instruments have already taken licenses for the new 5Kf core, which is the latest addition to MIPS Technologies' family of high-performance, 64bit synthesisable cores
This article was originally published on Electronicstalk on 23 Feb 2001 at 8.00am (UK)
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It is the industry's only licensable, synthesisable 64bit core with an integrated floating-point unit (FPU).
With features like an FPU and a dual-issue pipeline to increase processing throughput, the 5Kf core meets the growing demand for high-quality graphics and streaming media in next-generation digital consumer applications.
For example, it yields significant benefits in set-top box applications that require high-quality audio compression/decompression algorithms.
"A 64bit processor is a necessity when it comes to handling the demands of next-generation set-top boxes, which combine often disparate features such as high processing power and low power consumption, and right now, only MIPS Technologies is meeting that demand", said Tassos Markas, director of multimedia at Atmel.
The new 64bit core will be used by Atmel to enable its set-top boxes with broadband entertainment features such as video-on-demand, streaming video and audio, and interactive TV and cable telephony.
Features of the 5Kf core include:?390MHz typical performance; integer and floating point (peak) performance of 585Dhrystone MIPS (estimated) and 780MFLOPS; power consumption of 1.3-1.5mW/MHz (core only); 0-64Kbyte writeback data cache; 0-64Kbyte instruction cache; and a memory management unit with translation lookaside buffer.
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