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News Release from: MIPS Technologies | Subject: MIPS32 and MIPS64
Edited by the Electronicstalk Editorial
Team on 18 October 2001
Upgraded cores for faster performance at
low power
MIPS Technologies has upgraded its industry-standard MIPS32 and MIPS64 microprocessor RISC architectures.
MIPS Technologies has upgraded its industry-standard MIPS32 and MIPS64 microprocessor RISC architectures The new enhancements will increase processor efficiency and performance while cutting system power and costs in future implementations
This article was originally published on Electronicstalk on 12 Nov 2001 at 8.00am (UK)
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As the foundation for next-generation MIPS-based processor-related development, the enhanced architectures will support all legacy IP and will be fully compatible with the extensive lineup of third-party tools, operating systems and application software supporting the MIPS architecture.
Enhanced MIPS32 and MIPS64 architectures assure increased efficiency and performance on a seamless path from 32 to 64bit, while reducing power and lowering the cost of MIPS-based systems.
Interrupt processing will be faster and more efficient with general-purpose register (GPR) shadow sets, which will eliminate the need to save and restore GPRs when servicing an exception or interrupt.
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The shadow sets will reduce interrupt latencies by reducing register save time to just a pipeline flush.
Vectored interrupts are an additional enhancement to the architectures.
They minimise the processing required to determine the interrupt cause prior to interrupt handling.
Vectored interrupts can save up to 20 cycles, significantly reducing interrupt latency and increasing a processor's capability to manage millions of interrupts per second.
This additional speed and efficiency will be welcome in most designs, particularly high-performance network applications, set-top boxes and embedded automotive controls.
Enhanced bit-field manipulations will improve performance by allowing efficient manipulation of bits within data packets and/or device registers.
Bit field and other processing functions can be greatly accelerated by faster insert and extract fields, rotate and byte swap.
This will enhance performance in all embedded designs, especially embedded control (such as hard disk drives), and high-speed communications using TCP/IP or other communication protocols.
Enhanced coprocessor support will allow fully functional MIPS64-compliant coprocessors, such as floating processor units (FPU), to be combined with a 32bit central processing unit (CPU), thereby cutting the cost of demanding applications by teaming the optimum mix of CPU and coprocessor.
An enhanced MMU will be capable of managing pages as small as 1Kbyte or as large as 256Mbyte.
Support for smaller page sizes benefits both memory-constrained applications such as smart mobile devices and larger network applications where page size granularity is becoming a problem.
Very large page support allows entire regions of virtual memory to be mapped with a single translation lookaside buffer (TLB) entry allowing, for example, network applications to map and protect an entire memory resident database.
Finally, the evolving complexity of memory hierarchy demands additional standardisation support in future (OS) implementations.
MIPS Technologies is addressing this need by defining a mechanism in the architecture to indicate the presence and characteristics of L2 and L3 caches.
The new architectural enhancements will simplify and standardise the underlying mechanisms that will be used in supporting real-time software, assuring the continued availability and investment protection of standard development tools, operating systems and applications for MIPS-based solutions.
This also will lower costs and speed the development of new tools for the MIPS processor market.
The MIPS32 and MIPS64 architectures with these enhancements are available for licensing today.
The first implementation from MIPS Technologies, an ultra-low-power 32bit core, will follow in the first half of 2002.
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