64bit hard core comes on stream

What is claimed to be the embedded processor industry's highest performance licensable processor core is now available to customers for design starts.

What is claimed to be the embedded processor industry's highest performance licensable processor core is now available to customers for design starts.

The 64bit 600MHz MIPS64 20Kc hard core at a 0.13-micron fabrication process achieves performance of 1370 Dhrystone 2.1 MIPS (with inlining).

The 20Kc microarchitecture is scalable to 1GHz in a 0.10-micron process.

The core already is available at 400MHz in TSMC's 0.18-micron process.

The superscalar 20Kc core gives semiconductor suppliers and OEMs the highest system performance available for cost- and power-sensitive applications such as multimedia home gateways, automotive telematics, networking, office automation and game consoles.

The core's processing power allows systems designers to reduce end product cost by integrating in software many features traditionally handled by dedicated hardware blocks.

The 20Kc core also meets and exceeds emerging standards and feature requirements in applications such as set-top boxes, residential gateways and high-end printers.

"The MIPS64 20Kc core provides the most flexible capability to deliver performance due to its proven clock frequency and its implementation of the MIPS 64-bit ISA", said Cary Snyder, senior analyst at MicroDesign Resources and senior editor of Microprocessor Report.

"We have just dramatically reduced the time to market for designers of the most sophisticated SoCs for the next generation of systems", said Keith Diefendorff, vice president of product strategy at MIPS Technologies.

"The 20Kc core is the industry's highest performance licensable hard core, but it still offers the low-power characteristics and low overall system cost that are so important for embedded applications.

It is fully compatible with our 32bit core family, giving our customers a seamless migration path to the higher performance world of 64bit processing.

They also have access to a total system solution, including major operating systems, development tools and software applications".

The 20Kc core features a dual-issue, superscalar, seven-stage pipeline.

MIPS claims its integer and floating-point performance unprecedented for a licensable core.

Its 64bit dual-issue integer capability and double-precision IEEE-754 floating-point unit (FPU) allow the core to achieve a performance of 1370 Dhrystone 2.1 MIPS (with inlining) and peak 2.4 GFLOPS at 600MHz.

The use of SIMD (single-instruction, multiple data) instructions in the FPU greatly accelerate the processing of large data streams, eliminating the need for a separate DSP and thereby lowering the cost of the end product.

Power dissipation is low: 1.5W for the full core at 600MHz, at 1.0V.

And the core size is a small 8mm2.

With two 32Kbyte caches, memory management unit and floating-point unit, core size is 20mm2.

The 20Kc core also features a new, high-bandwidth interface, the MGB Link, to help eliminate performance bottlenecks.

This gives designers an industry-leading, peak 3.6Gbyte/s interface in an SoC environment - a significant benefit when moving very large data streams and graphics files.

The MGB Link is designed to scale to meet future throughput needs by allowing for wider bus widths and higher clock speeds.

MIPS Technologies held an online technical seminar on 12th February in which Keith Diefendorff and Liam Madden, vice president of high-performance processors, showed how to design embedded SoCs using the 20Kc core.

The presentation will be archived for six months on the MIPS website.

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