Product category:
Intellectual Property Cores
News Release from: MIPS Technologies | Subject: MIPS32 M4K
Edited by the Electronicstalk Editorial
Team on 01 May 2002
Core optimised for use in
multiprocessing SoCs
MIPS Technologies has developed a novel 32bit synthesisable core designed to optimise SoC designs implemented with multiple CPU cores.
MIPS Technologies has developed a novel 32bit synthesisable core designed to optimise SoC designs implemented with multiple CPU cores The emerging trend in multi-CPU SoCs addresses the rapidly increasing bandwidth requirements in next-generation broadband and networking devices
This article was originally published on Electronicstalk on 25 Sep 2007 at 8.00am (UK)
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The flexibility and re-programmability enables upgrades in software as protocol specifications or market requirements evolve.
Applications for the M4K core include data plane processing, as well as deeply embedded control processors, networked storage, residential gateways, set-top boxes and smart mobile devices.
Further reading
TSMC delivers hard core processors for MIPS fans
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In response to customer demand for a 64bit synthesisable processor core with floating point, MIPS Technologies has introduced the MIPS64 5Kf core.
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"Multi-CPU SoCs are required to meet the high-bandwidth demands of advanced networking equipment", said Linley Gwennap, principal analyst of The Linley Group.
"Modern IC process technology easily supports many CPUs on a single chip; the problem lies in connecting and debugging such complex designs.
The M4K core provides an efficient and effective solution to this problem while maintaining compatibility with the industry-standard MIPS instruction set and toolchain".
The M4K core features a typical clock speed over 300MHz, yet minimum power consumption is only 0.10mW/MHz, and core size is as small as 0.3mm2 in 0.13-micron processes.
It features code compression to reduce memory size, and it is the first core to use the MIPS32 architecture enhancements announced last October.
These include bit field instructions for easier handling of packet information, support for vectored interrupts to decrease interrupt latency, and multiple register sets for faster context switching.
Multi-CPU designs, in particular, benefit from the core's high-speed cacheless SRAM interface, user-defined instruction-set extensions to create highly differentiated features and optimise performance, and support for easy multi-CPU simulation and debug.
For networking applications, the M4K core is code-compatible with MIPS-based 64bit processors in the control plane, which gives networking system engineers more flexibility to allocate functions performed by the data plane and control plane processors to boost processing efficiency.
Features of the synthesisable M4K core include: typical performance of 300MHz, 405DMIPS (0.13-micron generic process); optimised cacheless SRAM interface that enables deterministic performance and reduces die size; five-stage pipeline that allows most instructions to execute in one cycle; MIPS16e code compression that reduces memory requirements by as much as 40%; packet manipulating bit instructions for packet header and deep-packet examinations and editing; vectored interrupts that reduce latency; up to four general-purpose register sets for fast context switching; a fast multiply/divide unit; enhanced JTAG (EJTAG) with PC and data trace support for easy multi-CPU debugging; and seamless, upward compatibility with MIPS64-based cores.
"The M4K core is the first core based on an industry-standard architecture to have user-defined instruction-set extensions.
It is also the first to include the enhanced MIPS32 architecture, which offers faster and more flexible packet processing and low-cost interrupt handling", said Kevin Meyer, vice president of marketing at MIPS Technologies.
"The M4K core also comes with a robust multi-CPU design environment that enables SoC designers to optimise their designs and quickly bring them to market".
The M4K core is supported by a rich environment of software and hardware tools for multi-CPU design and verification.
These include MIPS Technologies' bus-functional model and MIPSsim instruction-set simulator, and a complete offering of third-party development tools.
The MIPS32 M4K core is available now for licensing.
General availability is scheduled for the third quarter of 2002.
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