System controllers put cores to efficient use

MIPS Technologies reckons its new system controller family will enable SoC designers to increase overall system performance for next-generation applications and accelerate SoC development.

MIPS Technologies has a new system controller family that complements the high performance of MIPS processor cores, enabling SoC designers to increase overall system performance for next-generation applications and accelerate SoC development.

SOC-it system controllers have already been licensed to several customers, including NEC and leading providers of networking, satellite communications and set-top box solutions.

The SOC-it system controller family is one more step in MIPS Technologies' strategy to offer system platforms that enable customers to get to market faster with higher performance system-level products.

SOC-it system controllers feature an integrated memory controller optimised to take full advantage of the MIPS core in the SoC design.

They also include multiple, high-bandwidth, dual-port interfaces to IP (intellectual property) blocks and modular bridges that provide access to industry-standard buses and customer IP.

The result is a complete system-level solution that offers significantly higher performance than other standard system controllers, up to 100% memory bandwidth efficiency, and very low memory latency.

"High-bandwidth features and functionality such as digital streaming media that enhance a user's experience are creating a huge demand for higher system performance in a broad range of embedded systems.

The SOC-it controller family delivers that performance by giving our customers a very flexible, cost-effective, industry-standard solution for quickly moving very high volumes of data across the entire SOC platform", said Kevin Meyer, vice president of marketing at MIPS Technologies.

SOC-it system controllers increase system performance largely by means of an integrated memory controller and multiple, high-bandwidth IP interfaces.

The memory controller is optimised for, and closely coupled with, the MIPS core in the SoC.

It delivers up to 100% memory bandwidth efficiency, and latency is as low as 8-1-1-1 system clocks.

In addition, it supports industry-standard DRAM interfaces, including PC100 and PC133 for cost-sensitive applications, and DDR200 and DDR266 for high-performance applications.

Three dual-port IP interfaces offer high-bandwidth, point-to-point switched bus interconnects.

The dual-port design concept, traditionally found in high-performance SRAM, is a rarity in SoCs; and point-to-point interconnects typically are only found in very high-performance network switches.

They are featured in SOC-it controllers because they enable the CPU to access a peripheral while another peripheral simultaneously accesses the memory controller, unlike solutions that use a nonscalable, shared bus architecture.

Also included are modular bridges to industry-standard buses such as AMBA AHB and PCI that help preserve customers' existing IP blocks.

SOC-it controllers are synthesisable and available in five upgradable configurations: SOC-it EC-32 Lite and SOC-it EC-64 Lite system controllers, which are optimised for the MIPS32 4K and 4KE and MIPS64 5K core families, include a single-datarate (SDR) memory controller, interrupt controller, three dual-port IP interfaces, an AHB interface, and a peripheral bus controller; SOC-it EC-32 Deluxe and SOC-it EC-64 Deluxe controllers offer the same features as SOC-it Lite controllers plus double-datarate (DDR) support in the memory controller and PCIbus bridges; SOC-it MGB Deluxe controller offers the same features as SOC-it EC-32/64 Deluxe controllers but optimised for the highest performance MIPS core, the MIPS64 20Kc, which includes the MGB bus.

All versions of the SOC-it system controllers are available now.

(This was Electronicstalk's Top Story on 30 July 2002).

(This was Electronicstalk's Top Story on 30 July 2002).

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