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News Release from: MIPS Technologies | Subject: 20Kc core
Edited by the Electronicstalk Editorial
Team on 24 January 2003
Benchmarks prove speedy core performance
MIPS Technologies has published its certified EEMBC benchmark scores for the MIPS64 20Kc core, running at 600MHz against all five of EEMBC's application-based benchmark suites.
MIPS Technologies has published its certified Embedded Microprocessor Benchmark Consortium (EEMBC) benchmark scores for the MIPS64 20Kc core, running at 600MHz against all five of EEMBC's application-based benchmark suites EEMBC, a non-profit organisation, works collaboratively with member companies such as MIPS Technologies to develop performance benchmarks for key embedded applications - telecommunications, consumer, networking, office automation, and automotive/industrial
This article was originally published on Electronicstalk on 23 Feb 2001 at 8.00am (UK)
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EEMBC's benchmarks are based on the fundamental algorithms and functions of these applications and represent workloads that provide good metrics for comparing system performance.
The MIPS64 20Kc test chip running at a core operating frequency of 600MHz and using a compiler from Green Hills Software, received the following consolidated scores in out-of-the-box (Version 1.1) benchmark tests: 10.20 Telemarks; 39.42 Consumermarks; 10.62 Netmarks; 519.87 OAmarks; and 401.34 Automarks.
"We are delighted with the publication of the 20Kc scores for the MIPS architecture, one of the most widely adopted and broadly used architectures available.
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By publishing its certified benchmark scores, MIPS has provided engineers an objective means of evaluating its technology and validated the system-level performance achievable with the 20Kc core", said Markus Levy, EEMBC President.
"EEMBC provides out-of-the-box performance analysis for standard products like the 20Kc.
Other licensees of the MIPS architecture who have published their EEMBC scores include IDT, Intrinsity, NEC, and Toshiba".
The 20Kc core is the fastest licensable embedded microprocessor IP available, with a typical operating frequency of 600MHz and a worst case operating frequency of 533MHz at TSMC's 0.13um process technology node.
Its availability as a full custom hardened processor core from multiple foundries enables semiconductor companies to quickly get to market with an advanced high performance SoC design, while working with their choice of available foundry processes.
The 20Kc is an implementation of the MIPS64 instruction set architecture and a full dual issue superscalar machine implementing a seven-stage pipeline.
It includes an IEEE754 compliant SIMD floating-point-unit (FPU) with MIPS-3D graphics extensions.
The 20Kc core can execute two integer instructions or one integer and one floating point instruction per cycle.
At an operating frequency of 600MHz, the core delivers 1020DMIPS of integer performance (Version 2.1, no inlining), 2.4GFLOPS peak floating-point performance, and 30M polygons/s of geometry processing performance.
This core is an ideal processor solution for high performance applications in digital consumer and networking segments such as laser printers in office automation, high-speed line cards, routers and cellular base-stations in networking, network storage devices and high-end digital consumer devices including integrated Telematics systems for vehicles and digital televisions.
"The results of our EEMBC benchmarks confirm that the 20Kc core is ideally suited for applications that demand exceptional performance.
When combined with our SOC-it system controller, the challenges faced by high-end SoC designers are greatly simplified", said Brad Holtzinger, Director of System Solutions at MIPS Technologies.
Detailed score reports on the MIPS64 20Kc core are available for free from the 'Search Benchmark Scores' area of the EEMBC website (www.eembc.org).
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