Microarchitecture aims for SoC dominance

A new high-performance microarchitecture aims to address the changing economics of SoC design and help engineers increase profitability by extending their products' lifecycles.

MIPS Technologies has unveiled a new high-performance microarchitecture that will address the changing economics of SoC design and help engineers increase profitability by extending their products' lifecycles.

The MIPS32 24K microarchitecture is the foundation for MIPS Technologies' next-generation of high-performance, synthesisable cores, and extends the company's leadership as the provider of industry-standard performance technology to semiconductor and system companies.

The economics of SoC design are rapidly changing as process technologies migrate to 0.13um and below causing fixed design costs, such as mask sets, to explode.

As a result, system companies are under increasing pressure to maximise profitability by extending their products' time in market without new silicon spins.

Using high performance, programmable technology, such as the MIPS32 24K microarchitecture, SoC designers can leverage falling transistor costs to implement hardwired functionality in software.

"The high performance and programmable capabilities offered by the 24K microarchitecture enable system designers to add the features that their customers demand in software instead of using expensive mask sets", said Mike Uhler, CTO for MIPS Technologies.

"Combined with the more than 20 years of software development around the industry-standard MIPS architecture, customers can leverage the investment in operating systems, optimised protocol stacks and tool chains to reduce overall product development costs while getting to market faster".

The MIPS32 24K microarchitecture is well suited for next-generation embedded devices, such as digital consumer devices like set-top boxes and digital televisions, where high levels of system performance and application configurability are required.

Furthermore, the 24K microarchitecture meets the emerging service demands in broadband access and evolving networking infrastructure protocols that require software programmability.

The new microarchitecture from MIPS Technologies was designed based on feedback from market-leading customers who are looking to offer new feature rich products to the digital consumer and networking market segments.

It is designed to scale beyond 0.13um process technologies and features the latest architectural enhancements and configurable features from MIPS Technologies while maintaining compatibility with the industry-standard MIPS32 architecture.

"The 24K microarchitecture was designed in response to our customers' need for synthesisable and high-performance solutions", said Jack Browne, Vice President of Worldwide Sales.

"The name of the game is getting a differentiated product to market ahead of the competitionand the 24K microarchitecture enables our customers to do just that".

The new MIPS32 24K microarchitecture is ideal for products requiring high frequency operation on a low power budget.

As with all MIPS-based technologies, it offers broad tool and software support only available to products based on an industry-standard architecture.

Scalable performance features include: a single-issue eight-stage pipeline; operating performance ranges from 400 to 550MHz (worst case) in a 0.13um processes; an architecture designed for scalability beyond 0.13um technology nodes; hardware-based cache coherency to support multiprocessor scaling; configurable memory management unit with TLB or fixed mapping; and a 64bit high-performance memory subsystem with up to six outstanding read transactions.

It features the Release 2 implementation of the MIPS32 architecture with features such as multiple general purpose register sets and support for vectored interrupts, reduced interrupt latency and code compression technology with MIPS16eT ASE.

The microarchitecture fits industry-standard SoC construction methodologies as it is fully synthesisable and incorporates OCP high-speed point-to-point on-chip interconnect.

"MIPS Technologies has recognised that the economics of silicon are changing, and extending a product's time in market is critical to profitability", said Will Straus, founder and President of Forward Concepts.

"The 24K microarchitecture is a direct response to these trends, bringing high performance and programmability to solve the business challenges of next-generation SoC design".

"The 24K microarchitecture is a welcome addition to the SoC market.

We're pleased to be part of this exciting new offering", said Christopher Smith, Vice President of Marketing for Green Hills Software.

Green Hills Software will provide development tools and operating system support for Topaz.

"Green Hills products and cores based on the 24K microarchitecture provide a winning combination and will significantly benefit customers facing the challenges of next-generation SoC design", continued Uhler from MIPS Technologies.

"I am pleased to see the continuing momentum of OCP reflected in MIPS Technologies' strategic adoption of OCP in their new microarchitecture", said Ian Mackintosh, President of OCP-IP.

"The wide range of IP available and the tools infrastructure provided by OCP-IP make it a natural choice for high-end embedded designs".

"WindRiver and MIPS Technologies have a long history of developing optimised platform solutions for the digital consumer and networking markets", said Larry MacFarlane, general manager of the network infrastructure group for Wind River Systems.

"The high-performance 24K microarchitecture is ideally suited to address the needs of our customers within these target markets.

Together, 24K and our WindRiver Platforms will further speed the time-to-market parameters of our customers, while reducing risk and overall product cost".

Core derivates based on the MIPS32 24K microarchitecture will be available to early access customers by the fourth calendar quarter of 2003, and available for general licensing in the first calendar quarter of 2004.

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