Product category:
Intellectual Property Cores
News Release from: MIPS Technologies | Subject: MT ASE
Edited by the Electronicstalk Editorial
Team on 20 October 2003
Multithreading boosts processor
efficiency
The MIPS MT ASE (application specific extension) is a new multithreading extension to the industry-standard MIPS architecture.
The MIPS MT ASE (application specific extension) is a new multithreading extension to the industry-standard MIPS architecture Now, SoC designers are able to significantly increase delivered system performance through higher processor efficiency in applications that can take advantage of a multitasking approach to SoC design
This article was originally published on Electronicstalk on 23 Feb 2001 at 8.00am (UK)
Related stories
MIPS at the core of advanced smart cards
New from MIPS Technologies, the MIPS32 4KSc smart card core is a high-performance, synthesisable embedded 32bit processor core for ultra-low-power advanced smart card applications.
TSMC delivers hard core processors for MIPS fans
MIPS Technologies has announced the availability of "hard core" versions of its MIPS32 4Kc and 4Km 32bit processor cores.
Additionally, dedicated IP (such as DSPs) can be eliminated, lowering system costs by migrating more independent functions onto a single MT enabled MIPS-based core.
The MIPS MT ASE is tailored toward silicon companies doing MIPS-based designs, and makes the MIPS32 and MIPS64 architectures the only ones within the embedded industry to offer a full spectrum of solutions for SoC customers.
Today's feature-rich devices are incorporating more and more functionality to deliver an enhanced user experience.
Further reading
64bit soft core has integral floating-point unit
In response to customer demand for a 64bit synthesisable processor core with floating point, MIPS Technologies has introduced the MIPS64 5Kf core.
Boosted performance for 32bit soft core
MIPS Technologies has launched its next generation 32bit, high-performance, low-power core, the MIPS32 4KE family.
MIPS cores join Synopsis IP library
More than 25,000 design engineers who use the Synopsys DesignWare IP library to jump-start their designs will soon have access to the MIPS Technologies highly configurable MIPS32 4KE family of synthes
However, traditional single processor approaches cannot take advantage of the inherent parallelism these applications exhibit, such as parallel data operations to process audio and video algorithms, and shared multitasking compute environments.
This trend is forcing semiconductor companies to exploit techniques such as multithreading to increase overall system performance by enabling processors to share unused CPU resources across multiple threads of data.
The result is increased processor efficiency: concurrent data streams run in less time, and/or the same amount of work can be done on a smaller number of processors.
"The introduction of multithreading to the well known MIPS architecture is nothing less than the beginning of a new dynasty for multithreading RISC processors", said Jim Turley, technology analyst and Editor of the Silicon Insider.
"This is a big milestone in the 20-year history of important advancements to the MIPS architecture.
It adds a whole new set of features to MIPS-based designs that could potentially enable new types of applications".
"Multithreading squeezes more performance out of the same number of clock cycles to deliver greater processor efficiency", stated Tony Massimini, Chief Technology Officer of Semico Research.
"At the same time, companies can reduce die area and, therefore, overall costs and power consumption of their design.
The bonus benefit, of course, is that this solution is based on an industry-standard architecture that enables users to tap into broad third-party software support for fast adoption".
"The MIPS multithreading ASE is the next step toward helping our customers realise a greater level of silicon efficiency and cost effectiveness on an industry-standard architecture", said Victor Peng, Vice President of engineering for MIPS Technologies.
"This new architectural extension adds to our broad range of IP solutions, such as the M4K core, that customers can use for single-chip multiprocessing SoCs".
The MIPS MT ASE brings multithreading to an industry-standard architecture, enabling customers doing embedded multitasking designs to protect future investments and leverage the broad range of hardware and software support for the MIPS architecture.
Uniquely, the MIPS MT ASE incorporates two levels of multithreading capability.
First, virtual processing elements enable two virtual processors to share common resources, while still appearing to be independent cores to the software base.
This software transparency protects existing investments in operating systems and applications, yet allows a second virtual processor to run an independent thread delivering increased processor efficiency.
Secondly, using new instructions added to the MIPS32 and MIPS64 architectures, fine grain threading enables applications using MIPS MT ASE instructions to exploit inherent application parallelism.
Processors designed to take advantage of these instructions can, in simple RISC operations, spawn and control independent threads that share existing hardware.
These threads are then scheduled dynamically by hardware, dramatically raising processing efficiency.
The MIPS MT ASE also incorporates QoS (quality of service) scheduling.
This capability allows one or more real-time threads of execution to be allocated to a defined portion of the total compute power of a multithreaded processor.
Applying MIPS MT ASE QoS scheduling to MIPS-based CPUs enhanced with the CorExtend function for intensive media processing, solves major real-time scheduling problems of DSP-enhanced RISC processors.
Using a MIPS32 24Kc core, an SoC designer can reduce silicon real estate by as much as 46% when compared with a multicore solution.
For example, in a video decompression engine the application can be split across multiple cores, each processing a video segment.
The inherent data parallelism of this application is leveraged by the processors delivering increased system performance.
Multithreading allows the same or better performance with the 46% silicon area savings, preserving the SMP software model.
In today's SoCs, control plane functions are separated from data plane functions as the latter require known latencies and performance characteristics that are difficult to generate when shared by a common processor.
The MIPS MT ASE allows guaranteed allocation of processor bandwidth to specific tasks, where in the case of a merged control and data plane, it is possible to guarantee 75% of the processor cycles to the data task, while allowing the less time-critical control plane functions to fill the remaining time.
The MIPS MT ASE will be available for licensing by MIPS32 and MIPS64 ISA customers.
Additionally, this technology will appear in future 32 and 64bit cores developed by MIPS Technologies.
• MIPS Technologies: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
