Product category:
Intellectual Property Cores
News Release from: MIPS Technologies | Subject: MIPS32 24KT family
Edited by the Electronicstalk Editorial
Team on 31 March 2004
Core performance verified
The performance of the MIPS32 24KT family of processors has been verified using the Mentor Graphics VStationTBX verification accelerator.
The performance of the MIPS32 24KT family of processors, which operates from 400 to 550MHz worst case in a 0.13um process, was verified using the Mentor Graphics VStationTBX verification accelerator By using best-in-class technology from companies such as Mentor Graphics, MIPS Technologies is helping customers meet their performance targets using a 24K core
This article was originally published on Electronicstalk on 23 Feb 2001 at 8.00am (UK)
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"With Mentor Graphics' verification accelerator, we were able to boot both Linux and the Windows CE.NET operating systems.
We ran thousands of tests and 1.8 billion random verification cycles per day while still meeting our internal delivery schedule.
With this level of verification quality, we are delivering a 24K core that is proven, solid and reliable", said Don Ramsey, Director of CAD Operations at MIPS Technologies.
Further reading
64bit soft core has integral floating-point unit
In response to customer demand for a 64bit synthesisable processor core with floating point, MIPS Technologies has introduced the MIPS64 5Kf core.
Boosted performance for 32bit soft core
MIPS Technologies has launched its next generation 32bit, high-performance, low-power core, the MIPS32 4KE family.
"MIPS Technologies has used Mentor Graphics acceleration and emulation products for several years", said Eric Selosse, Vice President and General Manager of the Mentor Emulation Division.
"We are pleased that MIPS Technologies is reaping the performance benefits of our latest verification accelerator products for the development of their newest and most advanced processor family".
Mentor Graphics is a technology leader in high-performance hardware-assisted design verification tools.
With the VStationTBX system, MIPS Technologies created ultrafast transaction-level testbenches that reduced HDL regression testing time by 1000 times.
By compiling behavioural Verilog code into high-performance testbenches, VStationTBX reduced the time and effort to achieve acceleration.
The VStationTBX accelerator is used like a simulator, increasing verification productivity three to five times by eliminating cosimulation bottlenecks and using existing testbench setups.
As Mentor's third generation transaction-based product, the VStationTBX accelerator increases design efficiency by providing a scalable testbench methodology from software simulation to hardware acceleration.
In addition to supporting development of the 24K core family, Mentor Graphics is supporting customers of the 24K core family through its Seamless hardware/software coverification processor support package (PSP).
Mentor's Seamless PSP enables SoC designers to shave months off the development of their 24K core-based systems and ensure optimum performance by creating a virtual prototype of their design prior to physical hardware availability.
Both, the Seamless and the VStationTBX products, are tools of the Mentor Graphics Scalable Verification platform, a comprehensive electronic design automation (EDA) vendor tool platform for functional verification.
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