OCP system controller boosts SoC performance

A new SOC-it OCP system controller optimised for the MIPS32 24K core family enables SoC designers to dramatically increase overall system performance when compared with competing offerings.

A new SOC-it OCP system controller optimised for the MIPS32 24K core family enables SoC designers to dramatically increase overall system performance when compared with competing offerings.

The result is a complete system-level solution that offers up to 100% memory bandwidth efficiency and very low subsystem memory latency.

The SOC-it OCP system controller seamlessly connects to a 24K core and is MIPS Technologies' latest addition to its SOC-it family.

It features a tightly coupled memory controller and multiple, high bandwidth, dual-port interfaces to intellectual property (IP) blocks.

Using the SOC-it OCP system controller, designers also can reduce development time by using modular bridges to industry-standard buses.

"SoC designers who need to keep costs down while adding more features and functionality to demanding consumer applications have an ideal solution in an optimised system controller for our high performance 24K cores", said Russ Bell, Vice President of Marketing at MIPS Technologies.

"The SOC-it OCP controller offers a highly flexible, cost-effective means for moving massive amounts of data through an SoC at very high speeds".

"The challenges of increasingly complex SoC design demand standard buses and interfaces, and OCP is helping to make plug-and-play SoC design a reality".

"Standard interconnect interfaces are critical in meeting the challenges of increasingly complex SoC design and shrinking market windows", said Ian Mackintosh, President of OCP-IP.

"We are delighted to have OCP featured as the native interface in MIPS Technologies' new system controller for the 24K core family".

Modular, flexible and scalable SOC-it system controllers make it easy to meet the needs of higher performance, next-generation applications.

Features include an integrated memory controller that is optimised for, and closely coupled with, the MIPS-based CPU core in SoC designs.

It supports industry-standard DRAM interfaces to deliver up to 100% memory bandwidth efficiency and latency as low as 8-1-1-1 system clocks.

Dual-port IP interfaces and point-to-point switched bus interconnects offer a significant performance advantage over a shared bus architecture by enabling the CPU to access a device while another peripheral simultaneously accesses the SDRAM through the memory controller.

Support for vectored interrupts with software examples for interrupt handlers speed software development, and the flexible memory arbiter can be modified to prioritise data packets.

* Full compliance to industry-standard buses to preserve existing IP blocks.

* A fully static design that enables low-power operation to extend battery life in portable applications.

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