Product category:
Intellectual Property Cores
News Release from: MIPS Technologies | Subject: MIPS32 24K
Edited by the Electronicstalk Editorial
Team on 16 September 2004
Cores gain validated reference
methodology
Magma Design Automation and MIPS Technologies have developed a validated reference methodology for the high-performance MIPS32 24K microprocessor core family.
Magma Design Automation and MIPS Technologies have developed a validated reference methodology for the high-performance MIPS32 24K microprocessor core family The reference methodology is based on the Magma Blast Create RTL-to-placed gates, Blast Plan Pro hierarchical design and the Blast Fusion physical design solutions
This article was originally published on Electronicstalk on 20 Jun 2003 at 8.00am (UK)
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MIPS Technologies has revealed further details of the highest performing 32bit synthesisable core family within the embedded market.
The methodology includes flow documentation, floor-planning information, tool scripts and make files.
With a validated reference methodology, mutual customers are assured that the 24K core family can be easily integrated into SoC designs being implemented with Magma software.
The 24K core family is the highest performing synthesisable 32bit microprocessor family in the embedded industry.
Further reading
Seamless support for synthesisable processor cores
The Mentor Graphics Seamless hardware/software coverification processor support package (PSP) is now available for the the MIPS32 24K family.
Support for top-performing cores
Green Hills Software's comprehensive set of software development tools for MIPS-based applications now supports the new MIPS32 24K core family.
Core performance verified
The performance of the MIPS32 24KT family of processors has been verified using the Mentor Graphics VStationTBX verification accelerator.
It offers up to 625MHz performance in a 0.13-micron process, optimised design flows from leading EDA suppliers such as Magma, system-level on-chip interconnects and broad support from third party companies.
In addition to validating the reference flow, MIPS Technologies has completed the Magma IP verification process for the 24K family and the company has been added to the growing list of "Magma-ready" IP providers.
"Working with companies such as Magma, 24K core licensees will be assured access to front-to-back end flows from the leaders of the EDA industry", said Russ Bell, Vice President of Marketing at MIPS Technologies.
"We also are very pleased to participate in Magma's IP programme and with the growing relationship between our companies".
"We congratulate MIPS Technologies on the rapid success of the 24K product line and welcome them as a Magma-ready IP provider", said Michael Ma, Vice President, Foundry and IP Relationships for Magma.
"With the addition of MIPS Technologies to this programme, Magma and its partners will be working to provide Magma-ready versions for over 90% of the available processor cores".
At Magma's third annual users' group conference, MIPS Technologies will discuss details of the Magma reference flow for the 24K core family.
The Music conference will be held in Santa Clara, California, and is open to all Magma user companies.
Magma is offering customers of the 24K core family the Magma reference methodology with the relevant synthesis scripts and floor-planning information.
Support for the reference methodology is also provided by Magma.
The MIPS32 24K core family includes the 24Kc, 24Kc Pro, 24Kf and 24Kf Pro versions.
Tailored SoC design methodologies, an open core protocol (OCP) interconnect structure, standard libraries and on-chip memories from industry-leading companies help speed time-to-market, an important advantage for a processor core suited to embedded consumer applications such as digital and interactive TVs, set-top boxes and DVD players.
Magma has designed comprehensive soft and hard IP verification processes to enable fast deployment of partner IP products in IC designs.
Through the MagmaTies programme, partners are given access to Magma software, allowing them to meet the necessary requirements.
To qualify, soft IP providers such as MIPS must support Blast Create with industry-standard Verilog and VHDL formats and the most popular synthesis pragmas.
They must also be able to import constraints and verify the quality of results (QoR), perform formal verification against a known good netlist, validate the timing using a static timing analyser and create a script and documentation for the product.
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