MIPS-based processors star at forum

Some of the most innovative embedded processors unveiled last week at Fall Processor Forum (FPF) are based on the MIPS architecture.

Some of the most innovative embedded processors unveiled last week at Fall Processor Forum (FPF) are based on the MIPS architecture.

Offering significantly higher performance, greater power efficiency, and lower system cost, they include products from leading semiconductor licensees of MIPS Technologies and from the company itself.

FPF, a conference that combines the former Microprocessor and Embedded Processor Forums, is one of the largest annual technology events addressing new processor-related technologies.

Broadcom Corp, Cavium Networks and PMC-Sierra made news at this year's event by taking advantage of MIPS Technologies' open, flexible business model, industry-standard architecture, and vast ecosystem of optimised software to develop leading-edge, multiple-core processors for next-generation networking and communications applications.

Broadcom's latest family of 64bit MIPS-based processors includes the industry's first gigahertz quad-core broadband processor, which delivers up to 10,000 Dhrystone MIPS, 100Gbit/s memory bandwidth, and 145Gbit/s I/O bandwidth in a low-power, single-chip solution.

Integrating multiple MIPS-based CPU cores onto a single chip achieves much higher aggregate performance compared to the use of multiple discrete cores, while dramatically reducing board space and power dissipation.

Broadcom's new dual- and quad-core processors are targeted at data networking and communications applications, as well as security, storage, 3G wireless infrastructure and high-density computing applications.

Cavium Networks introduced the industry's first single-chip network services processor (NSP) family, which uses as many as 16 MIPS64-based cnMIPS cores for Internet services, content and security processing.

According to the company, Octeon NSPs deliver integrated application performance of up to 10Gbit/s, with as much as a 5x benefit in cost, performance and power over existing solutions.

Today's implementations of higher layer applications processing require a myriad of chips, including control-plane processors, data-plane processors and coprocessors for Internet services and security.

But Octeon NSPs introduce a revolutionary new SoC architecture that integrates the functionality of these various types of processors onto a single chip.

PMC-Sierra's latest 64bit MIPS-powered multiprocessor is the 1.8GHz, dual-CPU RM11200.

The highly integrated multiprocessor matches up two newly designed 1.8GHz E11K CPU cores with multiple high-speed memory and I/O interfaces, including dual DDR2, dual PCI Express, quad Gigabit Ethernet ports, and HyperTransport, to address the high bandwidth requirements for next-generation networking, storage and communications equipment.

The RM11200 was designed to give customers the highest level of processing performance, low power and leading-edge integration for applications such as enterprise routers, storage systems and DSLAMs.

PMC-Sierra also announced its Open Source Network Computing (NC) initiative to enable rapid commercialisation of low-power thin client solutions for education, enterprise, self-service kiosks, retail displays, Internet cafes and advanced video-on-demand.

The company's open source NC solution, the PMC Xiao Hu, is a commercially available single-board thin client solution codeveloped with China's Tsinghua University, MIPS Technologies and ATI Technologies.

Compared with the traditional desktop PC approach, the combination of the PMC Xiao Hu board with Linux software and a MIPS-powered processor reduces power by over 90% and IT costs by 70%.

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